2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography (2008)
Aug. 10, 2008 to Aug. 10, 2008
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FDTC.2008.18
This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics.The purpose of these prototype circuits is to experience with the published ``implementation-level'' attacks(SPA, DPA, EMA, templates, DFA).We report our conclusions about the practicability of these attacks:which ones are the most simple to mount, and which ones require more skill, time, equipments, etc.The potential of FPGAs as security evaluation commodities at design time is also detailed.Then, we discuss about ``dual counter-measures'', that are meant to resist both passive and active attacks.This study started four years ago with TIMA (Grenoble), in the framework of the project MARS.We highlight some research directions towards dependable and cost-effective dual counter-measures.
S. Guilley, L. Sauvage, N. Selmane, R. Pacalet and J. Danger, "Silicon-level Solutions to Counteract Passive and Active Attacks," 2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography(FDTC), vol. 00, no. , pp. 3-17, 2008.