The Community for Technology Leaders
2009 Forum on Specification & Design Languages (FDL 2009) (2009)
Sophia Antipolis
Sept. 22, 2009 to Sept. 24, 2009
ISSN: 1636-9874
ISBN: 978-2-9530504-1-7
TABLE OF CONTENTS

A re-use methodology for formal SoC protocol compliance verification (Abstract)

Minh D. Nguyen , University of Kaiserslautern, Germany
Max Thalmaier , University of Kaiserslautern, Germany
Markus Wedler , University of Kaiserslautern, Germany
Dominik Stoffel , University of Kaiserslautern, Germany
Wolfgang Kunz , University of Kaiserslautern, Germany
Jorg Bormann , OneSpin Solutions GmbH, Munich, Germany
pp. 1-6

SMT-based stimuli generation in the SystemC Verification library (Abstract)

Robert Wille , Institute of Computer Science, University of Bremen, 28359, Germany
Daniel Grosse , Institute of Computer Science, University of Bremen, 28359, Germany
Finn Haedicke , Institute of Computer Science, University of Bremen, 28359, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 1-6

Rapid prototyping of a DVB-SH turbo decoder using high-level-synthesis (Abstract)

Marko Rossler , Circuit and System Design, Chemnitz University of Technology, Germany
Hailu Wang , Circuit and System Design, Chemnitz University of Technology, Germany
Ulrich Heinkel , Circuit and System Design, Chemnitz University of Technology, Germany
Nur Engin , Corporate I&T / Research, NXP Semiconductors, Eindhoven, The Netherlands
Wolfram Drescher , Mobile & Personal, PL Feature, NXP Semiconductors, Dresden, Germany
pp. 1-6

Mixed simulation kernels for high performance virtual platforms (Abstract)

Marius Monton , GreenSocs, Spain
Jordi Carrabina , Dpt. Microelectrònica, Universitat Autdnòma de Barcelona, Spain
Mark Burton , GreenSocs, Spain
pp. 1-6

Checkpoint and Restore for SystemC models (Abstract)

Marius Monton , GreenSocs, Spain
Jakob Engblom , Virtutech, Spain
Mark Burton , GreenSocs, Spain
pp. 1-6

Another take on functional system-level design and modeling (Abstract)

Tomasz Toczek , GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine universitaire - B.P. 46, 38402, Saint Martin d'Hères, France
Dominique Houzet , GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine universitaire - B.P. 46, 38402, Saint Martin d'Hères, France
Stephane Mancini , GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine universitaire - B.P. 46, 38402, Saint Martin d'Hères, France
pp. 1-6

Efficient approximately-timed performance modeling for architectural exploration of MPSoCs (Abstract)

Martin Streubuhr , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jens Gladigau , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Christian Haubelt , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
pp. 1-6

A VHDL-AMS modeling methodology for top-down/bottom-up design of RF systems (Abstract)

Torsten Maehne , Laboratoire de Systèmes Microélectroniques (LSM), École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Alain Vachoux , Laboratoire de Systèmes Microélectroniques (LSM), École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Frederic Giroud , Microelectronics Division, Centre Suisse d'Electronique et de Microtechnique SA (CSEM), Switzerland
Matteo Contaldo , Microelectronics Division, Centre Suisse d'Electronique et de Microtechnique SA (CSEM), Switzerland
pp. 1-7

A top-down approach for the design of low-power microsensor nodes for wireless sensor network (Abstract)

Guillaume Terrasson , ESTIA Recherche, ESTIA, Technopôle Izarbel, 64210 Bidart, France
Renaud Briand , ESTIA Recherche, ESTIA, Technopôle Izarbel, 64210 Bidart, France
Skandar Basrour , ESTIA Recherche, ESTIA, Technopôle Izarbel, 64210 Bidart, France
Valerie Dupe , ESTIA Recherche, ESTIA, Technopôle Izarbel, 64210 Bidart, France
pp. 1-6

DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code (Abstract)

H. Gregor Molter , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
Andre Seffrin , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
Sorin A. Huss , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
pp. 1-6

A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip (Abstract)

Adan Kohler , Institut für Technische Informatik, Universität Stuttgart, Germany
Martin Radetzki , Institut für Technische Informatik, Universität Stuttgart, Germany
pp. 1-4

Linking GENESYS application architecture modelling with platform performance simulation (Abstract)

Subayal Khan , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
Susanna Pantsar-Syvaniemi , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
Jari Kreku , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
Kari Tiensyrja , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
Juha-Pekka Soininen , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
pp. 1-6

IP-XACT components with abstract time characterization (Abstract)

Aamir Mehmood Khan , Aoste Project, I3S/INRIA, INRIA Sophia-Antipolis Méditerranée, France
Frederic Mallet , Aoste Project, I3S/INRIA, Université de Nice-Sophia Antipolis, France
Charles Andre , Aoste Project, I3S/INRIA, Université de Nice-Sophia Antipolis, France
Robert de Simone , Aoste Project, I3S/INRIA, INRIA Sophia-Antipolis Méditerranée, France
pp. 1-6
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