The Community for Technology Leaders
2009 Forum on Specification & Design Languages (FDL 2009) (2009)
Sophia Antipolis
Sept. 22, 2009 to Sept. 24, 2009
ISSN: 1636-9874
ISBN: 978-2-9530504-1-7
TABLE OF CONTENTS

High level synthesis using operation properties (PDF)

Jan Langer , Chemnitz University of Technology, Germany
Ulrich Heinkel , Chemnitz University of Technology, Germany
pp. 1-6

A re-use methodology for formal SoC protocol compliance verification (Abstract)

Minh D. Nguyen , University of Kaiserslautern, Germany
Max Thalmaier , University of Kaiserslautern, Germany
Markus Wedler , University of Kaiserslautern, Germany
Dominik Stoffel , University of Kaiserslautern, Germany
Wolfgang Kunz , University of Kaiserslautern, Germany
Jorg Bormann , OneSpin Solutions GmbH, Munich, Germany
pp. 1-6

RAT-based formal verification of QDI asynchronous controllers (PDF)

Khaled Alsayeg , TIMA Laboratory, CNRS - Grenoble INP - UJF, 46 avenue Félix Viallet, 38031 Cedex, FRANCE
Katell Morin-Allory , TIMA Laboratory, CNRS - Grenoble INP - UJF, 46 avenue Félix Viallet, 38031 Cedex, FRANCE
Laurent Fesquet , TIMA Laboratory, CNRS - Grenoble INP - UJF, 46 avenue Félix Viallet, 38031 Cedex, FRANCE
pp. 1-6

SMT-based stimuli generation in the SystemC Verification library (Abstract)

Robert Wille , Institute of Computer Science, University of Bremen, 28359, Germany
Daniel Grosse , Institute of Computer Science, University of Bremen, 28359, Germany
Finn Haedicke , Institute of Computer Science, University of Bremen, 28359, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359, Germany
pp. 1-6

ISIS: Runtime verification of TLM platforms (PDF)

Luca Ferro , TIMA Laboratory (CNRS-GrenobleINP-UJF), 46 Av. Félix Viallet - 38031 cedex - France
Laurence Pierre , TIMA Laboratory (CNRS-GrenobleINP-UJF), 46 Av. Félix Viallet - 38031 cedex - France
pp. 1-6

Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specifications (PDF)

F. Herrera , TEISA Dept., E.T.S.I. I.T., University of Cantabria, Avda. Los Castros s/n, 39005 Santander, Spain
E. Villar , TEISA Dept., E.T.S.I. I.T., University of Cantabria, Avda. Los Castros s/n, 39005 Santander, Spain
pp. 1-6

Exploration of embedded memories in SoCs using SystemC-based functional performance models (PDF)

Hans-Peter Loeb , Infineon Technologies, Munich, Germany
Christian Sauer , Cadence Design Systems, Munich, Germany
pp. 1-6

Design automation model for application-specific processors on reconfigurable fabric (PDF)

B. Kurumahmut , CASLAB, Computer Engineering Department, Bo¿aziçi University, ¿stanbul, Turkey
G. Kabukcu , CASLAB, Computer Engineering Department, Bo¿aziçi University, ¿stanbul, Turkey
R. Ghamari , CASLAB, Computer Engineering Department, Bo¿aziçi University, ¿stanbul, Turkey
A. Yurdakul , CASLAB, Computer Engineering Department, Bo¿aziçi University, ¿stanbul, Turkey
pp. 1-6

Rapid prototyping of a DVB-SH turbo decoder using high-level-synthesis (Abstract)

Marko Rossler , Circuit and System Design, Chemnitz University of Technology, Germany
Hailu Wang , Circuit and System Design, Chemnitz University of Technology, Germany
Ulrich Heinkel , Circuit and System Design, Chemnitz University of Technology, Germany
Nur Engin , Corporate I&T / Research, NXP Semiconductors, Eindhoven, The Netherlands
Wolfram Drescher , Mobile & Personal, PL Feature, NXP Semiconductors, Dresden, Germany
pp. 1-6

Transaction level modeling of an adaptive multi-standard and multi-application radio communication system (PDF)

A. Barreteau , Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, F-44000 France
S. Le Nours , Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, F-44000 France
O. Pasquier , Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, F-44000 France
JP. Calvez , Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, F-44000 France
pp. 1-6

Mixed simulation kernels for high performance virtual platforms (Abstract)

Marius Monton , GreenSocs, Spain
Jordi Carrabina , Dpt. Microelectrònica, Universitat Autdnòma de Barcelona, Spain
Mark Burton , GreenSocs, Spain
pp. 1-6

Checkpoint and Restore for SystemC models (Abstract)

Marius Monton , GreenSocs, Spain
Jakob Engblom , Virtutech, Spain
Mark Burton , GreenSocs, Spain
pp. 1-6

Another take on functional system-level design and modeling (Abstract)

Tomasz Toczek , GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine universitaire - B.P. 46, 38402, Saint Martin d'Hères, France
Dominique Houzet , GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine universitaire - B.P. 46, 38402, Saint Martin d'Hères, France
Stephane Mancini , GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine universitaire - B.P. 46, 38402, Saint Martin d'Hères, France
pp. 1-6

Efficient approximately-timed performance modeling for architectural exploration of MPSoCs (Abstract)

Martin Streubuhr , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jens Gladigau , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Christian Haubelt , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
Jurgen Teich , Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany
pp. 1-6

Optimizing HW/SW Co-simulation based on run-time model switching (PDF)

Michael Karner , Institute for Technical Informatics, Graz University of Technology, Austria
Christian Steger , Institute for Technical Informatics, Graz University of Technology, Austria
Reinhold Weiss , Institute for Technical Informatics, Graz University of Technology, Austria
Eric Armengaud , The Virtual Vehicle Competence Center (ViF), Graz, Austria
pp. 1-6

Fast and unified SystemC AMS - HDL simulation (PDF)

Yaseen Zaidi , Institute of Computer Technology, Vienna University of Technology, Austria
Christoph Grimm , Institute of Computer Technology, Vienna University of Technology, Austria
Jan Haase , Institute of Computer Technology, Vienna University of Technology, Austria
pp. 1-6

A VHDL-AMS modeling methodology for top-down/bottom-up design of RF systems (Abstract)

Torsten Maehne , Laboratoire de Systèmes Microélectroniques (LSM), École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Alain Vachoux , Laboratoire de Systèmes Microélectroniques (LSM), École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Frederic Giroud , Microelectronics Division, Centre Suisse d'Electronique et de Microtechnique SA (CSEM), Switzerland
Matteo Contaldo , Microelectronics Division, Centre Suisse d'Electronique et de Microtechnique SA (CSEM), Switzerland
pp. 1-7

Design of experiments for effective pre-silicon verification of automotive electronics (PDF)

Monica Rafaila , Automotive Power, Infineon AG, Neubiberg, Germany
Christian Decker , Automotive Power, Infineon AG, Neubiberg, Germany
Georg Pelz , Automotive Power, Infineon AG, Neubiberg, Germany
Christoph Grimm , Vienna University of Technology, Austria
pp. 1-6

A top-down approach for the design of low-power microsensor nodes for wireless sensor network (Abstract)

Guillaume Terrasson , ESTIA Recherche, ESTIA, Technopôle Izarbel, 64210 Bidart, France
Renaud Briand , ESTIA Recherche, ESTIA, Technopôle Izarbel, 64210 Bidart, France
Skandar Basrour , ESTIA Recherche, ESTIA, Technopôle Izarbel, 64210 Bidart, France
Valerie Dupe , ESTIA Recherche, ESTIA, Technopôle Izarbel, 64210 Bidart, France
pp. 1-6

HSPICE implementation of a numerically efficient model of CNT transistor (PDF)

Tom J Kazmierski , School of Electronics and Computer Science, University of Southampton, S017 1BJ, UK
Dafeng Zhou , School of Electronics and Computer Science, University of Southampton, S017 1BJ, UK
Bashir M Al-Hashimi , School of Electronics and Computer Science, University of Southampton, S017 1BJ, UK
pp. 1-5

A SystemC superset for high-level synthesis (PDF)

Maxim Smirnov , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA
Andres Takach , Mentor Graphics Corporation, 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA
pp. 1-6

EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications (PDF)

Bijoy A. Jose , FERMAT Lab, Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, 24061, USA
Jason Pribble , FERMAT Lab, Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, 24061, USA
Lemaire Stewart , FERMAT Lab, Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, 24061, USA
Sandeep K. Shukla , FERMAT Lab, Bradley Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, 24061, USA
pp. 1-6

DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code (Abstract)

H. Gregor Molter , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
Andre Seffrin , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
Sorin A. Huss , Integrated Circuits and Systems Lab, Technische Universität Darmstadt, Germany
pp. 1-6

Proposal to extend frequency domain analysis in VHDL-AMS (PDF)

Joachim Haase , Fraunhofer IIS/EAS, Dresden, Germany
Ewald Hessel , Hella KG aA Hueck & Co, Lippstadt, Germany
Heinz-Theo Mammen , Hella KG aA Hueck & Co, Lippstadt, Germany
pp. 1-4

A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip (Abstract)

Adan Kohler , Institut für Technische Informatik, Universität Stuttgart, Germany
Martin Radetzki , Institut für Technische Informatik, Universität Stuttgart, Germany
pp. 1-4

Transaction level modeling of a FlexRay communication network (PDF)

M. Cheikhwafa , Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, F-44000 France
S. Le Nours , Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, F-44000 France
O. Pasquier , Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, F-44000 France
JP. Calvez , Univ Nantes, IREENA, EA1770, Polytech-Nantes, rue C. Pauc, F-44000 France
pp. 1-4

Understanding physical models in VHDL-AMS (PDF)

Abdulhadi Shoufan , Center for Advanced Security Research Darmstadt CASED, Germany
Sorin Huss , Integrated Circuits and Systems Labs, TU-Darmstadt, Germany
pp. 1-4

Evaluation of SystemC-AMS modeling capabilities of RF front-end non-linearities: satellite receiver case study (PDF)

Rami Khouri , LEAT - CNRS - University of Nice UMR 6071, 06560 Valbonne-France
Benjamin Nicolle , LEAT - CNRS - University of Nice UMR 6071, 06560 Valbonne-France
Lucas Alves Da Silva , LEAT - CNRS - University of Nice UMR 6071, 06560 Valbonne-France
William Tatinian , LEAT - CNRS - University of Nice UMR 6071, 06560 Valbonne-France
Gilles Jacquemod , LEAT - CNRS - University of Nice UMR 6071, 06560 Valbonne-France
pp. 1-4

A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chip (PDF)

Alain Greiner , LIP6, Université Pierre et Marie Curie, 4 place Jussieu, 75252 Paris, France
Etienne Faure , LIP6, Université Pierre et Marie Curie, 4 place Jussieu, 75252 Paris, France
Nicolas Pouillon , LIP6, Université Pierre et Marie Curie, 4 place Jussieu, 75252 Paris, France
Daniela Genius , LIP6, Université Pierre et Marie Curie, 4 place Jussieu, 75252 Paris, France
pp. 1-4

Extension of SystemC framework towards power analysis (PDF)

M. Conti , DIBET, Università Politecnica delle Marche, Ancona, Italy
G. Vece , DIBET, Università Politecnica delle Marche, Ancona, Italy
S. Colazilli , DIBET, Università Politecnica delle Marche, Ancona, Italy
pp. 1-4

Analysis of sense finger dynamics for accurate ΣΔ MEMS accelerometer modelling in VHDL-AMS (PDF)

Chenxu Zhao , School of Electronics and Computer Science, University of Southampton, S017 1BJ, UK
Tom J Kazmierski , School of Electronics and Computer Science, University of Southampton, S017 1BJ, UK
pp. 1-4

SystemC-based power simulation of wireless sensor networks (PDF)

Jan Haase , Vienna University of Technology, Institute of Computer Technology, Gusshausstraße 27-29/E384, 1040 Wien, Austria
Markus Damm , Vienna University of Technology, Institute of Computer Technology, Gusshausstraße 27-29/E384, 1040 Wien, Austria
Johann Glaser , Vienna University of Technology, Institute of Computer Technology, Gusshausstraße 27-29/E384, 1040 Wien, Austria
Javier Moreno , Vienna University of Technology, Institute of Computer Technology, Gusshausstraße 27-29/E384, 1040 Wien, Austria
Christoph Grimm , Vienna University of Technology, Institute of Computer Technology, Gusshausstraße 27-29/E384, 1040 Wien, Austria
pp. 1-4

Semi-automated Hw/Sw Co-design for embedded systems: from MARTE models to SystemC simulators (PDF)

Luis Gabriel Murillo , ALaRI Institute, Faculty of Informatics, University of Lugano, Switzerland
Marcello Mura , ALaRI Institute, Faculty of Informatics, University of Lugano, Switzerland
Mauro Prevostini , ALaRI Institute, Faculty of Informatics, University of Lugano, Switzerland
pp. 1-6

Linking GENESYS application architecture modelling with platform performance simulation (Abstract)

Subayal Khan , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
Susanna Pantsar-Syvaniemi , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
Jari Kreku , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
Kari Tiensyrja , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
Juha-Pekka Soininen , Technical Research Centre of Finland (VTT), Kaitoväylä 1, FI-90571 Oulu, Finland
pp. 1-6

IP-XACT components with abstract time characterization (Abstract)

Aamir Mehmood Khan , Aoste Project, I3S/INRIA, INRIA Sophia-Antipolis Méditerranée, France
Frederic Mallet , Aoste Project, I3S/INRIA, Université de Nice-Sophia Antipolis, France
Charles Andre , Aoste Project, I3S/INRIA, Université de Nice-Sophia Antipolis, France
Robert de Simone , Aoste Project, I3S/INRIA, INRIA Sophia-Antipolis Méditerranée, France
pp. 1-6
84 ms
(Ver 3.3 (11022016))