2010 Fifth International Conference on Frontier of Computer Science and Technology (2010)
Changchun, Jilin Province, China
Aug. 18, 2010 to Aug. 22, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCST.2010.72
Most of the current dynamic binary translation (DBT) systems are single-threaded and many orders of magnitude slower than native execution. Although multi-core processors are becoming more and more prevalent, the single-threaded architecture prevents these DBT systems from improving their performance by making full use of the parallel execution advantage. In this paper, we present the design and implementation of a multi-threaded DBT system, named MT-BTRIMER. MT-BTRIMER employs a master-slave multi-threaded architecture. We evaluate the MT-BTRIMER system across SPEC CINT 2000 and BYTEmark test suite. The results demonstrate that MT-BTRIMER can speculatively translate on average 60% of useful target code, and reduce the total runtime by nearly 30% compared with ST-BTRIMER which is a single-threaded DBT system.
DBT, Multi-threaded, Master-Slave Architecture, Speculative Translation, Load Balance
Z. Yu, Y. Hu, X. Tu, H. Jin and J. Chen, "MT-BTRIMER: A Master-Slave Multi-threaded Dynamic Binary Translator," 2010 Fifth International Conference on Frontier of Computer Science and Technology(FCST), Changchun, Jilin Province, China, 2010, pp. 51-56.