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IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2013) (2013)
Seattle, WA
April 28, 2013 to April 30, 2013
ISBN: 978-1-4673-6005-0
TABLE OF CONTENTS

Reconfigurable computing in the era of post-silicon scaling [panel discussion] (PDF)

Eric Chung , Microsoft Research
Doug Burger , Microsoft Research
Mike Butts , Compute Forest
Jan Gray , Gray Research LLC
Chuck Thacker , Microsoft Research
Kees Vissers , Xilinx
John Wawrzynek , Univ. California at Berkeley, CA, USA
pp. xvi

Parallel Computation of Skyline Queries (Abstract)

Louis Woods , Dept. of Comput. Sci., ETH Zurich, Zurich, Switzerland
Gustavo Alonso , Dept. of Comput. Sci., ETH Zurich, Zurich, Switzerland
Jens Teubner , Dept. of Comput. Sci., DBIS Group, Tech. Univ. Dortmund, Dortmund, Germany
pp. 1-8

Minerva: Accelerating Data Analysis in Next-Generation SSDs (Abstract)

Arup De , Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
Maya Gokhale , Lawrence Livermore Nat. Lab., Livermore, CA, USA
Rajesh Gupta , Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
Steven Swanson , Dept. of Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
pp. 9-16

Accelerating Join Operation for Relational Databases with FPGAs (Abstract)

Robert J. Halstead , Dept. Comput. Sci., Univ. of California, Riverside, Riverside, CA, USA
Bharat Sukhwani , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Hong Min , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Mathew Thoennes , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Parijat Dube , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Sameh Asaad , IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Balakrishna Iyer , IBM Silicon Valley Lab., San Jose, CA, USA
pp. 17-20

Boosting Memory Performance of Many-Core FPGA Device through Dynamic Precedence Graph (Abstract)

Yu Bai , Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
Abigail Fuentes , Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
Michael Riera , Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
Mohammed Alawad , Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
Mingjie Lin , Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA
pp. 21-24

Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration (Abstract)

Christopher Dennl , Hardware/Software Co.-Design, Univ. of Erlangen-Nuremberg, Nuremberg, Germany
Daniel Ziener , Hardware/Software Co.-Design, Univ. of Erlangen-Nuremberg, Nuremberg, Germany
Jurgen Teich , Hardware/Software Co.-Design, Univ. of Erlangen-Nuremberg, Nuremberg, Germany
pp. 25-28

Accuracy-Performance Tradeoffs on an FPGA through Overclocking (Abstract)

Kan Shi , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
David Boland , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
George A. Constantinides , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
pp. 29-36

Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor (Abstract)

Alexander Brant , Dept. of ECE, Univ. of British Columbia, Vancouver, BC, Canada
Ameer Abdelhadi , Dept. of ECE, Univ. of British Columbia, Vancouver, BC, Canada
Douglas H. H. Sim , Dept. of ECE, Univ. of British Columbia, Vancouver, BC, Canada
Shao Lin Tang , Dept. of ECE, Univ. of British Columbia, Vancouver, BC, Canada
Michael Xi Yue , Dept. of ECE, Univ. of British Columbia, Vancouver, BC, Canada
Guy G. F. Lemieux , Dept. of ECE, Univ. of British Columbia, Vancouver, BC, Canada
pp. 37-44

Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices (Abstract)

Eddie Hung , Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada
Fatemeh Eslami , Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada
Steven J. E. Wilton , Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada
pp. 45-52

A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers (Abstract)

Madhura Purnaprajna , Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
Paolo Ienne , Ecole Polytech. Fed. de Lausanne (EPFL), Lausanne, Switzerland
pp. 53-56

Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits (Abstract)

Abdulazim Amouri , Inst. of Comput. Eng., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
Hussam Amrouch , Inst. of Comput. Eng., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
Thomas Ebi , Inst. of Comput. Eng., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
Jorg Henkel , Inst. of Comput. Eng., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
Mehdi Tahoori , Inst. of Comput. Eng., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
pp. 57-60

On-chip Context Save and Restore of Hardware Tasks on Partially Reconfigurable FPGAs (Abstract)

Aurelio Morales-Villanueva , Dept. of Electr. & Comput. Eng., Univ. of Florida Gainesville, Gainesville, FL, USA
Ann Gordon-Ross , Dept. of Electr. & Comput. Eng., Univ. of Florida Gainesville, Gainesville, FL, USA
pp. 61-64

A High Throughput No-Stall Golomb-Rice Hardware Decoder (Abstract)

Roger Moussalli , Dept. of Comput. Sci. & Eng., Univ. of California Riverside, Riverside, CA, USA
Walid Najjar , Dept. of Comput. Sci. & Eng., Univ. of California Riverside, Riverside, CA, USA
Xi Luo , Dept. of Comput. Sci. & Eng., Univ. of California Riverside, Riverside, CA, USA
Amna Khan , Dept. of Comput. Sci. & Eng., Univ. of California Riverside, Riverside, CA, USA
pp. 65-72

A Reconfigurable Architecture for 1-D and 2-D Discrete Wavelet Transform (Abstract)

Qing Sun , Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
Jiang Jiang , Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
Yongxin Zhu , Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
Yuzhuo Fu , Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
pp. 81-84

High Speed Video Processing Using Fine-Grained Processing on FPGA Platform (Abstract)

Zhi Ping Ang , Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore
Akash Kumar , Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore
Yajun Ha , Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore
pp. 85-88

The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs (Abstract)

Qijing Huang , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Ruolong Lian , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Andrew Canis , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Jongsok Choi , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Ryan Xi , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Stephen Brown , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Jason Anderson , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
pp. 89-96

Automating Elimination of Idle Functions by Run-Time Reconfiguration (Abstract)

Xinyu Niu , Dept. of Comput., Imperial Coll. London, London, UK
Thomas C. P. Chau , Dept. of Comput., Imperial Coll. London, London, UK
Qiwei Jin , Dept. of Comput., Imperial Coll. London, London, UK
Wayne Luk , Dept. of Comput., Imperial Coll. London, London, UK
Qiang Liu , Sch. of Electron. Inf. Eng., Tianjin Univ., Tianjin, China
pp. 97-104

Open-Source Bitstream Generation (Abstract)

Ritesh Kumar Soni , Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
Neil Steiner , Inf. Sci. Inst., Univ. of Southern California, Arlington, VA, USA
Matthew French , Inf. Sci. Inst., Univ. of Southern California, Arlington, VA, USA
pp. 105-112

PRML: A Modeling Language for Rapid Design Exploration of Partially Reconfigurable FPGAs (Abstract)

Rohit Kumar , NSF Center for High-Performance Reconfigurable Comput., Univ. of Florida, Gainesville, FL, USA
Ann Gordon-Ross , NSF Center for High-Performance Reconfigurable Comput., Univ. of Florida, Gainesville, FL, USA
pp. 117-120

Atacama: An Open FPGA-Based Platform for Mixed-Criticality Communication in Multi-segmented Ethernet Networks (Abstract)

Gonzalo Carvajal , Dept. of Electr. Eng. & Center for Opt. & Photonics, Univ. de Concepcion, Concepcion, Chile
Miguel Figueroa , Dept. of Electr. Eng. & Center for Opt. & Photonics, Univ. de Concepcion, Concepcion, Chile
Robert Trausmuth , Dept. of Embedded Syst., UAS Technikum Wien, Vienna, Austria
Sebastian Fischmeister , Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
pp. 121-128

Latency-Optimized Networks for Clustering FPGAs (Abstract)

Trevor Bunker , Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
Steven Swanson , Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA
pp. 129-136

A Range and Scaling Study of an FPGA-Based Digital Wireless Channel Emulator (Abstract)

Scott Buscemi , Adv. Commun. Technol. Lab., SPAWAR Syst. Center Atlantic, Charleston, SC, USA
Will Kritikos , Reconfigurable Comput. Syst. Lab., Univ. of North Carolina at Charlotte, Charlotte, NC, USA
Ron Sass , Reconfigurable Comput. Syst. Lab., Univ. of North Carolina at Charlotte, Charlotte, NC, USA
pp. 137-144

Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch (Abstract)

Asif Khan , MIT-CSAIL, Cambridge, MA, USA
Nirav Dave , SRI Int., Menlo Park, CA, USA
pp. 145-148

An FPGA Based PCI-E Root Complex Architecture for Standalone SOPCs (Abstract)

Yingjie Cao , Sch. of Microelectron., Shanghai Jiaotong Univ., Shanghai, China
Yongxin Zhu , Sch. of Microelectron., Shanghai Jiaotong Univ., Shanghai, China
Xu Wang , Sch. of Microelectron., Shanghai Jiaotong Univ., Shanghai, China
Jiang Jiang , Sch. of Microelectron., Shanghai Jiaotong Univ., Shanghai, China
Meikang Qiu , Dept. of Electr. & Comput. Eng., Univ. of Kentucky, Lexington, KY, USA
pp. 149-152

Application Composition and Communication Optimization in Iterative Solvers Using FPGAs (Abstract)

Abid Rafique , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
Nachiket Kapre , Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore
George A. Constantinides , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
pp. 153-160

Parallel Generation of Gaussian Random Numbers Using the Table-Hadamard Transform (Abstract)

David B. Thomas , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
pp. 161-168

Hardware-Software Codesign for Embedded Numerical Acceleration (Abstract)

Ranko Sredojevic , EECS, MIT, Cambridge, MA, USA
Andrew Wright , EECS, MIT, Cambridge, MA, USA
Vladimir Stojanovic , EECS, MIT, Cambridge, MA, USA
pp. 169-172

FAssem: FPGA Based Acceleration of De Novo Genome Assembly (Abstract)

B. Sharat Chandra Varma , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Delhi, New Delhi, India
Kolin Paul , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Delhi, New Delhi, India
M. Balakrishnan , Dept. of Comput. Sci. & Eng., Indian Inst. of Technol. Delhi, New Delhi, India
Dominique Lavenier , IRISA, INRIA, Rennes, France
pp. 173-176

Accelerating the Computation of Induced Dipoles for Molecular Mechanics with Dataflow Engines (Abstract)

Frederico Pratas , INESC-ID/IST, Lisbon, Portugal
Diego Oriato , Maxeler Technol., London, UK
Oliver Pell , Maxeler Technol., London, UK
Ricardo A. Mata , Inst. fur Phys. Chem., Univ. Gottingen, Gottingen, Germany
Leonel Sousa , INESC-ID/IST, Lisbon, Portugal
pp. 177-180

On Optimizing the Arithmetic Precision of MCMC Algorithms (Abstract)

Grigorios Mingas , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
Farhan Rahman , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
Christos-Savvas Bouganis , Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
pp. 181-188

Efficient Large Integer Squarers on FPGA (Abstract)

Simin Xu , Xilinx Asia Pacific, Singapore, Singapore
Suhaib A. Fahmy , Nanyang Technol. Univ., Singapore, Singapore
Ian V. McLoughlin , Univ. of Sci. & Technol. of China, Hefei, China
pp. 198-201

Elementary Function Implementation with Optimized Sub Range Polynomial Evaluation (Abstract)

Martin Langhammer , Altera Eur. Technol. Centre, High Wycombe, UK
Bogdan Pasca , Altera Eur. Technol. Centre, High Wycombe, UK
pp. 202-205

High-Level Description and Synthesis of Floating-Point Accumulators on FPGA (Abstract)

Marc-Andre Daigneault , Dept. of Electr. Eng., Ecole Polytech. de Montral, Montreal, QC, Canada
Jean Pierre David , Dept. of Electr. Eng., Ecole Polytech. de Montral, Montreal, QC, Canada
pp. 206-209

Reconfigurable Acceleration of Short Read Mapping (Abstract)

James Arram , Dept. of Comput., Imperial Coll. London, London, UK
Kuen Hung Tsoi , Dept. of Comput., Imperial Coll. London, London, UK
Wayne Luk , Dept. of Comput., Imperial Coll. London, London, UK
Peiyong Jiang , Dept. of Chem. Pathology, Chinese Univ. of Hong Kong, Hong Kong, China
pp. 210-217

An FPGA-Based Data Flow Engine for Gaussian Copula Model (Abstract)

Huabin Ruan , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Xiaomeng Huang , Center for Earth Syst. Sci., Tsinghua Univ., Beijing, China
Haohuan Fu , Center for Earth Syst. Sci., Tsinghua Univ., Beijing, China
Guangwen Yang , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Wayne Luk , Dept. of Comput. Eng., Imperial Coll. London, London, UK
Sebastien Racaniere , Maxeler Technol., London, UK
Oliver Pell , Maxeler Technol., London, UK
Wenjing Han , Sch. of Comput. Sci. & Technol., Harbin Inst. of Technol., Harbin, China
pp. 218-225

A Delay-based PUF Design Using Multiplexers on FPGA (Abstract)

Miaoqing Huang , Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA
Shiming Li , Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA
pp. 226

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits (Abstract)

Jiliang Zhang , Coll. of Inf. Sci. & Eng., Hunan Univ., Changsha, China
Yaping Lin , Coll. of Inf. Sci. & Eng., Hunan Univ., Changsha, China
Yongqiang Lyu , Res. Inst. of Inf. Technol., Tsinghua Univ., Beijing, China
Ray C. C. Cheung , Dept. of Electron. Eng., City Univ. of Hong Kong, Hong Kong, China
Wenjie Che , Coll. of Inf. Sci. & Eng., Hunan Univ., Changsha, China
Qiang Zhou , DCST, Tsinghua Univ., Beijing, China
Jinian Bian , DCST, Tsinghua Univ., Beijing, China
pp. 227

A Soft Coarse-Grained Reconfigurable Array Based High-level Synthesis Methodology: Promoting Design Productivity and Exploring Extreme FPGA Frequency (Abstract)

Cheng Liu , Dept. of Electr. & Electron. Eng., Univ. of Hong Kong, Hong Kong, China
Colin Lin Yu , Dept. of Electr. & Electron. Eng., Univ. of Hong Kong, Hong Kong, China
Hayden Kwok-Hay So , Dept. of Electr. & Electron. Eng., Univ. of Hong Kong, Hong Kong, China
pp. 228

FPGA Simulation Engine for Customized Construction of Neural Microcircuit (Abstract)

Jason Cong , Dept. of Comput. Sci., Univ. of California, Los Angeles, Los Angeles, CA, USA
Hugh T. Blair , Psychol. Dept., Univ. of California Los Angeles, Los Angeles, CA, USA
Di Wu , Dept. of Comput. Sci., Univ. of California, Los Angeles, Los Angeles, CA, USA
pp. 229

Global Atmospheric Simulation on a Reconfigurable Platform (Abstract)

Lin Gan , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Haohuan Fu , Minist. of Educ. Key Lab. for Earth Syst. Modeling, Tsinghua Univ., Beijing, China
Wayne Luk , Dept. of Comput., Imperial Coll. London, London, UK
Chao Yang , Inst. of Software, Beijing, China
Wei Xue , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Guangwen Yang , Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
pp. 230

An Approach to a Fully Automated Partial Reconfiguration Design Flow (Abstract)

Kizheppatt Vipin , Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore
Suhaib A. Fahmy , Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore, Singapore
pp. 231

A Multithreaded VLIW Soft Processor Family (Abstract)

Kalin Ovtcharov , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Ilian Tili , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
J. Gregory Steffan , Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
pp. 232

A Configurable Architecture for a Visual Saliency System and Its Application in Retail (Abstract)

Nandhini Chandramoorthy , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Siddarth Advani , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Kevin M. Irick , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Vijaykrishnan Narayanan , Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
pp. 233

The Impact of Hardware Communication on a Heterogeneous Computing System (Abstract)

Shanyuan Gao , Reconfigurable Comput. Syst. Lab., Univ. of North Carolina at Charlotte, Charlotte, NC, USA
Bin Huang , Reconfigurable Comput. Syst. Lab., Univ. of North Carolina at Charlotte, Charlotte, NC, USA
Ron Sass , Reconfigurable Comput. Syst. Lab., Univ. of North Carolina at Charlotte, Charlotte, NC, USA
pp. 234

An Evaluation of High-Performance Embedded Processing on MPPAs (Abstract)

Zain-ul-Abdin , Halmstad Univ., Halmstad, Sweden
Bertil Svensson , Halmstad Univ., Halmstad, Sweden
pp. 235

A Fast and Accurate FPGA-Based Fault Injection System (Abstract)

Thomas Schweizer , Comput. Eng., Eberhard Karls Univ. Tubingen, Tubingen, Germany
Dustin Peterson , Comput. Eng., Eberhard Karls Univ. Tubingen, Tubingen, Germany
Johannes M. Kuhn , Comput. Eng., Eberhard Karls Univ. Tubingen, Tubingen, Germany
Tommy Kuhn , Comput. Eng., Eberhard Karls Univ. Tubingen, Tubingen, Germany
Wolfgang Rosenstiel , Comput. Eng., Eberhard Karls Univ. Tubingen, Tubingen, Germany
pp. 236

Memory Access Scheduling on the Convey HC-1 (Abstract)

Zheming Jin , Dept. of Comput. Sci. & Eng., Univ. of South Carolina, Columbia, SC, USA
Jason D. Bakos , Dept. of Comput. Sci. & Eng., Univ. of South Carolina, Columbia, SC, USA
pp. 237

Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping (Abstract)

Marco Ceriani , DEIB, Politec. di Milano, Milan, Italy
Gianluca Palermo , DEIB, Politec. di Milano, Milan, Italy
Simone Secchi , DIEE, Univ. di Cagliari, Cagliari, Italy
Antonino Tumeo , Pacific Northwest Nat. Lab., Richland, WA, USA
Oreste Villa , Pacific Northwest Nat. Lab., Richland, WA, USA
pp. 238

Global Control and Storage Synthesis for a System Level Synthesis Approach (Abstract)

Shuo Li , Dept. of Electron. Syst., R. Inst. of Technol. (KTH), Stockholm, Sweden
Nasim Farahini , Dept. of Electron. Syst., R. Inst. of Technol. (KTH), Stockholm, Sweden
Ahmed Hemani , Dept. of Electron. Syst., R. Inst. of Technol. (KTH), Stockholm, Sweden
pp. 239
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