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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2012)
Toronto, Ontario Canada
Apr. 29, 2012 to May 1, 2012
ISBN: 978-0-7695-4699-5
pp: 184-187
The explosion of Next Generation Sequencing (NGS) data with over one billion reads per day poses a great challenge to the capability of current computing systems. In this paper, we proposed a CPU-FPGA heterogeneous architecture for accelerating a short reads mapping algorithm, which was built upon the concept of hash-index. In particular, by extracting and mapping the most time-consuming and basic operations to specialized processing elements (PEs), our new algorithm is favorable to efficient acceleration on FPGAs. The proposed architecture is implemented and evaluated on a customized FPGA accelerator card with a Xilinx Virtex5 LX330 FPGA resided. Limited by available data transfer bandwidth, our NGS mapping accelerator, which operates at 175MHz, integrates up to 100 PEs. Compared to an Intel six-cores CPU, the speedup of our accelerator ranges from 22.2 times to 42.9 times.
short reads mapping, FPGA, hash, accelerator

W. Wang et al., "Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator," Field-Programmable Custom Computing Machines, Annual IEEE Symposium on(FCCM), Toronto, Ontario Canada, 2012, pp. 184-187.
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