Poster abstracts (Abstract)

Title Page i (PDF)

Title Page iii (PDF)

[Copyright notice] (PDF)

Table of contents (PDF)

Message from the General Chairs (PDF)

Message from the Program Chairs (PDF)

Organization (PDF)

Steering Committee (PDF)

Program Committee (PDF)

Additional reviewers (PDF)

Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs (Abstract)

Accelerating the Nonuniform Fast Fourier Transform Using FPGAs (Abstract)

Increased Performace of FPGA-Based Color Classification System (Abstract)

Pipelined Hardware Architecture for High-Speed Optical Flow Estimation Using FPGA (Abstract)

Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive (Abstract)

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration (Abstract)

Energy-Aware Optimisation for Run-Time Reconfiguration (Abstract)

A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems (Abstract)

Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs (Abstract)

Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-Based FPGAs (Abstract)

Hardware Acceleration of Approximate Tandem Repeat Detection (Abstract)

Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence (Abstract)

Reaping the Processing Potential of FPGA on Double-Precision Floating-Point Operations: An Eigenvalue Solver Case Study (Abstract)

Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision (Abstract)

Blocking LU Decomposition for FPGAs (Abstract)

Acceleration of a DWT-Based Algorithm for Short Exposure Stellar Images Processing on a HPRC Platform (Abstract)

A TDMA Ethernet Switch for Dynamic Real-Time Communication (Abstract)

Designing Modular Hardware Accelerators in C with ROCCC 2.0 (Abstract)

SIRC: An Extensible Reconfigurable Computing Communication API (Abstract)

ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs (Abstract)

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research (Abstract)

Automated Precision Analysis: A Polynomial Algebraic Approach (Abstract)

FPGA Circuit Synthesis of Accelerator Data-Parallel Programs (Abstract)

Impulse C vs. VHDL for Accelerating Tomographic Reconstruction (Abstract)

Integrating High-Level Synthesis into MPI (Abstract)

Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems (Abstract)

BURAQ: A Dynamically Reconfigurable System for Stateful Measurement of Network Traffic (Abstract)

A Memory-Efficient and Modular Approach for String Matching on FPGAs (Abstract)

A Large-Scale Architecture for Restricted Boltzmann Machines (Abstract)

A Heterogeneous FPGA Architecture for Support Vector Machine Training (Abstract)

A High-Speed and Memory Efficient Pipeline Architecture for Packet Classification (Abstract)

FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures (Abstract)

Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance (Abstract)

Using the Power Side Channel of FPGAs for Communication (Abstract)

Design of a Reconfigurable Hybrid Database System (Abstract)

A Comparative Study on the Architecture Templates for Dynamic Nested Loops (Abstract)

A Scripting Engine for Combining Design Transformations (Abstract)

A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip (Abstract)

Enumeration of Bent Boolean Functions by Reconfigurable Computer (Abstract)

DPA Resistant AES on FPGA Using Partial DDL (Abstract)

Author Index (PDF)

[Publisher's information] (PDF)