A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip
2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (2010)
Charlotte, North Carolina, USA
May 2, 2010 to May 4, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2010.47
Until today, the efficient partitioning and mapping of applications for multiprocessor systems is a challenging task. The deployment of reconfigurable hardware in this domain helps to meet the application requirements more efficiently due to hardware adaptation at design and runtime, which is not applicable in the traditional multiprocessor domain. To exploit this novel degree of freedom in multiprocessor system-on-chip (MPSoC) technology, a novel design methodology is needed, which helps to hide the complexity of the hardware architecture and its realization alternatives from the developer. This paper shows one approach for such a design methodology for the development of the hardware architecture and the application partitioning and mapping. A novel multistep approach based on hierarchical clustering is used for partitioning of the software application and for configuration of a runtime adaptive multiprocessor system. Furthermore, each application module is then partitioned in a Hardware-Software Codesign process in order to achieve a maximum of performance on the local processors and therefore in general for the MPSoC.
Design Methodology, Toolchain, MPSoC, Partitioning, HW/SW Codesign, FPGA, Reconfigurable Computing
M. Benz, D. Göhringer, M. Hübner and J. Becker, "A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip," 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines(FCCM), Charlotte, North Carolina, USA, 2010, pp. 259-262.