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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2010)
Charlotte, North Carolina, USA
May 2, 2010 to May 4, 2010
ISBN: 978-0-7695-4056-6
pp: 179-182
One of the major impediments to deploying partially run-time reconfigurable FPGAs as hardware accelerators is the time overhead involved in loading the hardware modules. While configuration prefetching is an effective method that can be employed to reduce this overhead, mispredicted prefetches may worsen the situation by increasing the number of reconfigurations needed. In this paper, we present a static algorithm for configuration prefetching in partially reconfigurable FPGAs that minimizes the reconfiguration overhead. By making use of profiling, the interprocedural control flow graph, and the placement information of hardware modules, our algorithm predicts hardware execution and tries to prefetch hardware modules as early as possible while minimizing the risk of mis-predictions. Our experiments show that our algorithm performs significantly better than current state-of-the-art prefetching algorthms for control-bound applications.
FPGA, Interprocedural, Configuration Prefetching, Control-Flow, Compilers
Jürgen Teich, Weng-Fai Wong, Tobias Ziermann, Joon Edward Sim, Gregor Walla, "Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems", Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, vol. 00, no. , pp. 179-182, 2010, doi:10.1109/FCCM.2010.35
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