2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (2010)
Charlotte, North Carolina, USA
May 2, 2010 to May 4, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2010.17
Run-time reconfiguration has been shown to produce power and energy efficient designs. However, it is important to take into account the energy overhead of the reconfiguration process itself. This paper presents an analytical model that covers the effects of power consumption and configuration speed of the reconfiguration process. Based on this model, a method is introduced that establishes the optimal degree of parallelism for designs supporting partial run-time reconfiguration. Our energy-aware approach is illustrated by optimising designs for software-defined radio: a reconfigurable FIR filter is shown to be up to 49% more energy efficient and up to 87% more area efficient than a non-reconfigurable design.
FPGA, run-time reconfiguration, energy efficiency
W. Luk, P. Y. Cheung and T. Becker, "Energy-Aware Optimisation for Run-Time Reconfiguration," 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines(FCCM), Charlotte, North Carolina, USA, 2010, pp. 55-62.