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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2010)
Charlotte, North Carolina, USA
May 2, 2010 to May 4, 2010
ISBN: 978-0-7695-4056-6
pp: 29-32
This paper presents a hardware architecture for increased performance of color classification. In our architecture, color classification, based on an AdaBoost algorithm, identifies a pixel as having the color of interest or not. We designed the proposed architecture using Verilog HDL and implemented the design in a Xilinx Virtex-5 FPGA. The architecture for color classification can have 598 times performance improvement over an equivalent software solution and 1.9 times performance improvement over the leading hardware color classifier.
AdaBoost; architecture; color classification; FPGA; image processing; Verilog HDL
Junguk Cho, Bridget Benson, Sunsern Cheamanukul, Ryan Kastner, "Increased Performace of FPGA-Based Color Classification System", Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, vol. 00, no. , pp. 29-32, 2010, doi:10.1109/FCCM.2010.50
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