Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2010)
Charlotte, North Carolina, USA
May 2, 2010 to May 4, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/FCCM.2010.13
We present an FPGA accelerator for the Non-uniform Fast Fourier Transform, which is a technique to reconstruct images from arbitrarily sampled data. We accelerate the compute-intensive interpolation step of the NuFFT Gridding algorithm by implementing it on an FPGA. In order to ensure efficient memory performance, we present a novel FPGA implementation for Geometric Tiling based sorting of the arbitrary samples. The convolution is then performed by a novel Data Translation architecture which is composed of a multi-port local memory, dynamic coordinate-generator and a plug-and-play kernel pipeline. Our implementation is in single-precision floating point and has been ported onto the BEE3 platform. Experimental results show that our FPGA implementation can generate fairly high performance without sacrificing flexibility for various data-sizes and kernel functions. We demonstrate up to 8X speedup and up to 27 times higher performance-per-watt over a comparable CPU implementation and up to 20% higher performance-per-watt when compared to a relevant GPU implementation.
NuFFT, interpolation, convolution, BEE3, Geometric Tiling
Kevin M. Irick, Sungho Park, Vijaykrishnan Narayanan, Srinidhi Kestur, "Accelerating the Nonuniform Fast Fourier Transform Using FPGAs", Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, vol. 00, no. , pp. 19-26, 2010, doi:10.1109/FCCM.2010.13