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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2007)
Napa, California
Apr. 23, 2007 to Apr. 25, 2007
ISBN: 0-7695-2940-2
TABLE OF CONTENTS
Posters

A Configurable Processor Synthesis System (PDF)

C. Gloster , Howard Univ., USA
W. Gay , Howard Univ., USA
pp. 331-332
Introduction
Session 1: Applications

Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware (Abstract)

Wayne Luk , Imperial College London, UK
David B. Thomas , Imperial College London, UK
pp. 3-12

A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman Problem (Abstract)

Ioannis Papaefstathiou , Technical University of Crete, Greece
Ioannis Mavroidis , Technical University of Crete, Greece
Dionisios Pnevmatikatos , Technical University of Crete, Greece
pp. 13-22

On the Acceleration of Shortest Path Calculations in Transportation Networks (Abstract)

Maya Gokhale , Los Alamos National Lab, USA
Zachary K. Baker , Los Alamos National Lab, USA
pp. 23-34
Session 2: Software Tools

Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration (Abstract)

Wayne Luk , Imperial College London, UK
Peter Y.K. Cheung , Imperial College London, UK
Tobias Becker , Imperial College London, UK
pp. 35-44
Session 3: System

A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable Computing (Abstract)

Anthony Mark Jones , Ambric, Inc., Oregon, USA
Michael Butts , Ambric, Inc., Oregon, USA
Paul Wasson , Ambric, Inc., Oregon, USA
pp. 55-64

Configurable Transactional Memory (Abstract)

Chirstoforos Kachris , Delft University of Technology, The Netherlands; Xilinx Inc., USA
Chidamber Kulkarni , Xilinx Inc., USA
pp. 65-72

A Reconfigurable Hardware Interface for a Modern Computing System (Abstract)

Katherine Compton , University of Wisconsin-Madison, USA
Philip Garcia , University of Wisconsin-Madison, USA
pp. 73-84
Session 4: Bioinformatics

FPGA Acceleration of Gene Rearrangement Analysis (Abstract)

Jason D. Bakos , University of South Carolina, USA
pp. 85-94

FPGA-accelerated seed generation in Mercury BLASTP (Abstract)

Arpith Jacob , Washington University in St. Louis, USA
Jeremy Buhler , Washington University in St. Louis, USA
Roger D. Chamberlain , Washington University in St. Louis, USA; BECS Technology, Inc., USA
Joseph Lancaster , Washington University in St. Louis, USA
pp. 95-106
Session 5: Scientific Computing

Systolic Architecture for Computational Fluid Dynamics on FPGAs (Abstract)

Takanori Iizuka , Tohoku University, Japan
Satoru Yamamoto , Tohoku University, Japan
Kentaro Sano , Tohoku University, Japan
pp. 107-116

FPGA-Based Multigrid Computation for Molecular Dynamics Simulations (Abstract)

Martin C. Herbordt , Boston University, USA
Yongfeng Gu , Boston University, USA
pp. 117-126

Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing (Abstract)

Andrew G. Schmidt , University of North Carolina at Charlotte, USA
Parag Beeraka , University of North Carolina at Charlotte, USA
William V. Kritikos , University of North Carolina at Charlotte, USA
Ron Sass , University of North Carolina at Charlotte, USA
Srinivas Beeravolu , University of North Carolina at Charlotte, USA
pp. 127-140
Session 6: Applications

Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs (Abstract)

Christos-S Bouganis , Imperial College London, UK
Peter Y.K. Cheung , Imperial College London, UK
Iosifina Pournara , University of London, UK
pp. 141-150

K-means Clustering for Multispectral Images Using Floating-Point Divide (Abstract)

Xiaojun Wang , Northeastern University, Boston, USA
Miriam Leeser , Northeastern University, Boston, USA
pp. 151-162
Session 7: Floating Point Arithmetic

Optimizing Logarithmic Arithmetic on FPGAs (Abstract)

Oskar Mencer , Imperial College London, UK
Haohuan Fu , Imperial College London, UK
Wayne Luk , Imperial College London, UK
pp. 163-172

Generating FPGA-Accelerated DFT Libraries (Abstract)

Markus Puschel , Carnegie Mellon University, USA
Franz Franchetti , Carnegie Mellon University, USA
Peter A. Milder , Carnegie Mellon University, USA
Aliaksei Sandryhaila , Carnegie Mellon University, USA
James C. Hoe , Carnegie Mellon University, USA
Jose M.F. Moura , Carnegie Mellon University, USA
pp. 173-184

An FPGA implementation of pipelined multiplicative division with IEEE Rounding (Abstract)

Guy Even , Tel-Aviv University, Israel
Ronen Goldberg , Tel-Aviv University, Israel
Peter-M. Seidel , Southern Methodist University, USA
pp. 185-196
Session 8: Applications

Integer Factorization Based on Elliptic Curve Method: Towards Better Exploitation of Reconfigurable Hardware (Abstract)

Francois Gosset , UCL/DICE Crypto Group, Belgium
Jean-Jacques Quisquater , UCL/DICE Crypto Group, Belgium
Giacomo de Meulenaer , UCL/DICE Crypto Group, Belgium
Guerric Meurice de Dormale , UCL/DICE Crypto Group, Belgium
pp. 197-206

Matched Filter Computation on FPGA, Cell and GPU (Abstract)

Zachary K. Baker , Los Alamos National Laboratory, USA
Maya B. Gokhale , Los Alamos National Laboratory, USA
Justin L. Tripp , Los Alamos National Laboratory, USA
pp. 207-218
Session 9: Software Tools II

A Data-Driven Approach for Pipelining Sequences of Data-Dependent Loops (Abstract)

Rui Rodrigues , INESC-ID, Portugal
Joao M.P. Cardoso , INESC-ID, Portugal; Universidade Tecnica de Lisboa, Portugal
Pedro C. Diniz , INESC-ID, Portugal; Universidade Tecnica de Lisboa, Portugal
pp. 219-228

Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware (Abstract)

Laurie Smith King , College of the Holy Cross, USA
Nicholas Moore , Northeastern University, Boston, USA
Albert Conti , Northeastern University, Boston, USA
Miriam Leeser , Northeastern University, Boston, USA
pp. 229-238

Mitrion-C Application Development on SGI Altix 350/RC100 (Abstract)

Robert J. Brunner , University of Illinois at Urbana-Champaign, USA
Adam D. Myers , University of Illinois at Urbana-Champaign, USA
Volodymyr V. Kindratenko , University of Illinois at Urbana-Champaign, USA
pp. 239-250
Session 10: Optimization

Automatic On-chip Memory Minimization for Data Reuse (Abstract)

Peter Y.K. Cheung , Imperial College, UK
Konstantinos Masselos , University of Peloponnese, Greece
Qiang Liu , Imperial College, UK
George A. Constantinides , Imperial College, UK
pp. 251-260

Scientific Application Acceleration with Reconfigurable Functional Units (Abstract)

Kyle Rupnow , University of Wisconsin-Madison, USA; Sandia National Lab
Katherine Compton , University of Wisconsin-Madison, USA
Keith Underwood , Sandia National Lab
pp. 261-274
Posters

Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment (Abstract)

Khaled Benkrid , The University of Edinburgh, Scotland
Abdsamad Benkrid , The University of Edinburgh, Scotland
Ying Liu , The University of Edinburgh, Scotland
pp. 275-278

The Case for Dynamic Execution on Dynamic Hardware (PDF)

Wim Bohm , Colorado State University, USA
Charles Ross , Colorado State University, USA
pp. 279-280

On Solving RC5 Challenges with FPGAs (PDF)

Jean-Jacques Quisquater , UCL/DICE Crypto Group, Belgium
John Bass , DMS Design, USA
Guerric Meurice de Dormale , UCL/DICE Crypto Group, Belgium
pp. 281-282

Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-Chip (PDF)

N.W. Bergmann , The University of Queensland, Australia
C.M. Wee , The University of Queensland, Australia
P.R. Sutton , The University of Queensland, Australia
pp. 283-284

A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic (PDF)

Hiroshi Shinohara , Kumamoto University, Japan
Hideaki Monji , Kumamoto University, Japan
Toshinori Sueyoshi , Kumamoto University, Japan
Masahiro Iida , Kumamoto University, Japan
pp. 285-286

New Protection Mechanisms for Intellectual Property in Reconfigurable Logic (PDF)

Tim Guneysu , Ruhr University Bochum Germany
Bodo Moller , Ruhr University Bochum Germany
Christof Paar , Ruhr University Bochum Germany
pp. 287-288

Establishing Chain of Trust in Reconfigurable Hardware (PDF)

Christof Paar , Horst Gortz Institute for IT Security, Germany
Ahmad-Reza Sadeghi , Horst Gortz Institute for IT Security, Germany
Thomas Eisenbarth , Horst Gortz Institute for IT Security, Germany
Russell Tessier , University of Massachusetts Amherst, USA
Marko Wolf , Horst Gortz Institute for IT Security, Germany
Tim Guneysu , Horst Gortz Institute for IT Security, Germany
pp. 289-290

Hand-based Interface for Augmented Reality (PDF)

J. Manuel Ferrandez-Vicente , Univ. Politecnica de Cartagena, Spain
J. Javier Martinez-Alvarez , Univ. Politecnica de Cartagena, Spain
F. Javier Toledo-Moreo , Univ. Politecnica de Cartagena, Spain
pp. 291-292

Discrete-Time Cellular Neural Networks in FPGA (PDF)

J. Javier Martinez-Alvarez , Univ. Politecnica de Cartagena Cuartel de Antiguones, Spain
F. Javier Toledo-Moreo , Univ. Politecnica de Cartagena Cuartel de Antiguones, Spain
J. Manuel Ferrandez-Vicente , Univ. Politecnica de Cartagena Cuartel de Antiguones, Spain
pp. 293-294

Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs (PDF)

Fernando Moraes , PUCRS, Brazil
L. Torres , LIRMM, France
G. Sassatelli , LIRMM, France
Ismael Augusto Grehs , PUCRS, Brazil
Cristiane Woszezenki , PUCRS, Brazil
N. Saint-Jean , LIRMM, France
P. Benoit , LIRMM, France
M. Robert , LIRMM, France
pp. 295-296

Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems (PDF)

Tughrul Arslan , Institute for System Level Integration, UK; University of Edinburgh, UK
Ahmet Erdogan , Institute for System Level Integration, UK; University of Edinburgh, UK
Ioannis Nousias , University of Edinburgh, UK
Nazish Aslam , Institute for System Level Integration, UK
Mark Milward , University of Edinburgh, UK
pp. 297-298

Software/Hardware Co-Scheduling for Reconfigurable Computing Systems (PDF)

Tarek El-Ghazawi , The George Washingtong University, USA
Proshanta Saha , The George Washingtong University, USA
pp. 299-300

Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures (Abstract)

Ahmet T. Erdogan , University of Edinburgh, UK
Tughrul Arslan , University of Edinburgh, UK
Ioannis Nousias , University of Edinburgh, UK
Han Wei , University of Edinburgh, UK
Mark Muir , University of Edinburgh, UK
pp. 301-304

Abstracting Modern FCCMs To Provide a Single Interface to Architectural Resources (Abstract)

Graham Schelle , University of Colorado at Boulder, USA
Dirk Grunwald , University of Colorado at Boulder, USA
pp. 305-308

A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable Logic (PDF)

Hiroshi Shinohara , Kumamoto University, Japan
Toshinori Sueyoshi , Kumamoto University, Japan
Masahiro Iida , Kumamoto University, Japan
Hideaki Monji , Kumamoto University, Japan
pp. 309-310

Heterogeneous Floorplanner for FPGA (PDF)

Elaheh Bozorgzadeh , University of California, Irvine, USA
Love Singhal , University of California, Irvine, USA
pp. 311-312

Automatic Self-Reconfiguration of System-on-Chip Peripherals (Abstract)

John A. Williams , The University of Queensland, Australia
Neil W. Bergmann , The University of Queensland, Australia
Yi Lu , The University of Queensland, Australia
pp. 313-316

A Hybrid Memory Sub-system for Video Coding Applications (PDF)

Wayne Luk , Imperial College, UK
Peter Cheung , Imperial College, UK
Su-Shin Ang , Imperial College, UK
George Constantinides , Imperial College, UK
pp. 317-318

Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog Array (PDF)

David V. Anderson , Georgia Institute of Technology, USA
Paul Hasler , Georgia Institute of Technology, USA
Brian Gestner , Georgia Institute of Technology, USA
Chris Twigg , Georgia Institute of Technology, USA
Sung Kyu Lim , Georgia Institute of Technology, USA
Faik Baskaya , Georgia Institute of Technology, USA
pp. 319-320

PixelStreams-based implementation of videodetector (PDF)

Miroslaw Jablonski , AGH University of Science and Technology, Poland
Marek Gorgon , AGH University of Science and Technology, Poland
Jaromir Przybylo , AGH University of Science and Technology, Poland
Piotr Pawlik , AGH University of Science and Technology, Poland
pp. 321-322

Design Space Exploration for the BLAST Algorithm Implementation (Abstract)

Euripides Sotiriades , Technical University of Crete, Greece
Apostolos Dollas , Technical University of Crete, Greece
pp. 323-326

An Integrated Video Compression, Encryption and Information Hiding Architecture based on the SCAN Algorithm and the Stretch Technology (Abstract)

A. Dollas , Technical University of Crete, Greece; Wright State University, USA
S. Mertoguno , CGO Inc., USA
N. Bourbakis , Wright State University, USA
G. Chrysos , Technical University of Crete, Greece
pp. 327-330

Low-Cost Stereo Vision on an FPGA (PDF)

Chris Murphy , Franklin W. Olin College of Engineering, USA
Mark L. Chang , Franklin W. Olin College of Engineering, USA
Ann Marie Rynning , Franklin W. Olin College of Engineering, USA
Daniel Lindquist , Franklin W. Olin College of Engineering, USA
Sarah Leavitt , Franklin W. Olin College of Engineering, USA
Thomas Cecil , Franklin W. Olin College of Engineering, USA
pp. 333-334

Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration Overhead (PDF)

Apostolos Dollas , Technical University of Crete, Greece
Antonis Anyfantis , Technical University of Crete, Greece
Kyprianos Papadimitriou , Technical University of Crete, Greece
pp. 335-336

Quantifying Effective Memory Bandwidth of Platform FPGAs (PDF)

Ron Sass , University of North Carolina, Charlotte, USA
Andrew G. Schmidt , University of Kansas, USA
pp. 337-338

A Flexible Filter Processor for Fading Channel Simulation (Abstract)

Amirhossein Alimohammad , University of Alberta, Canada
Bruce F. Cockburn , University of Alberta, Canada
Christian Schlegel , University of Alberta, Canada
Saeed Fouladi Fard , University of Alberta, Canada
pp. 339-342

RBoot: Software Infrastructure for a Remote FPGA Laboratory (PDF)

Ron Sass , University of North Carolina, Charlotte, USA
Kushal Datta , University of North Carolina, Charlotte, USA
pp. 343-344

Jumble: A Hardware-in-the-Loop Simulation System for JHDL (Abstract)

David Castells-Rufas , Universitat Autonoma de Barcelona, Spain
Jordi Carrabina , Universitat Autonoma de Barcelona, Spain
pp. 345-348

Sparse Matrix-Vector Multiplication Design on FPGAs (Abstract)

Junqing Sun , University of Tennessee, USA
Gregory Peterson , University of Tennessee, USA
Olaf Storaasli , Oak Ridge National Laboratory, USA
pp. 349-352

Changing Output Quality for Thermal Management (PDF)

John W. Lockwood , Washington University, USA
Phillip H. Jones , Washington University, USA
James Moscola , Washington University, USA
Young H. Cho , Washington University, USA
pp. 353-354

Hardware/Software co-design of a key point detector on FPGA (PDF)

F. Muhlbauer , Kaiserslautern University of Technology, Germany
K. Berns , Kaiserslautern University of Technology, Germany
T. Braun , Kaiserslautern University of Technology, Germany
C. Bobda , Kaiserslautern University of Technology, Germany
H. Djakou Chati , Kaiserslautern University of Technology, Germany
pp. 355-356
Author Index

Author Index (PDF)

pp. 357
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