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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2006)
Napa, California
Apr. 24, 2006 to Apr. 26, 2006
ISBN: 0-7695-2661-6
TABLE OF CONTENTS
Session 1: Supercomputer Applications

A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer (Abstract)

Viktor K. Prasanna , University of Southern California Los Angeles, CA
Richard D. Anderson , Jackson State University Jackson, MS
Gerald R. Morris , University of Southern California Los Angeles, CA
pp. 3-12

A case study in porting a production scientific supercomputing application to a reconfigurable computer (Abstract)

David Pointer , University of Illinois at Urbana-Champaign
Volodymyr Kindratenko , University of Illinois at Urbana-Champaign
pp. 13-22

Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers (Abstract)

Maya Gokhale , Los Alamos National Laboratory, Los Alamos, NM
Frans Trouw , Los Alamos National Laboratory, Los Alamos, NM
Viktor K. Prasanna , University of Southern California, Los Angeles, CA
Ronald Scrofano , University of Southern California, Los Angeles, CA
pp. 23-34
Session 2: Methodology and Tools

Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs (Abstract)

C.H. Ho , Imperial College London, UK
P.H.W. Leong , Imperial College London, UK
S.J.E. Wilton , University of British Columbia, Canada
W. Luk , Imperial College London, UK
S. Lopez-Buedo , Universidad Autonoma de Madrid, Spain
pp. 35-44
Session 3: Data Generation and Processing

Efficient Hardware Generation of Random Variates with Arbitrary Distributions (Abstract)

Wayne Luk , Imperial College London
David B. Thomas , Imperial College London
pp. 57-66

An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems (Abstract)

Zachary K. Baker , University of Southern California, Los Angeles, CA, USA
Viktor K. Prasanna , University of Southern California, Los Angeles, CA, USA
pp. 67-75

Automatic Sliding Window Operation Optimization for FPGA-Based (Abstract)

Miriam Leeser , Northeastern University, Boston, MA, USA
Haiqian Yu , Northeastern University, Boston, MA, USA
pp. 76-88
Session 4: Hybrid Systems

Enabling a Uniform Programming Model Across the Software/Hardware Boundary (Abstract)

Ron Sass , University of Kansas, Lawrence, KS
David Andrews , University of Kansas, Lawrence, KS
Ed Komp , University of Kansas, Lawrence, KS
Wesley Peck , University of Kansas, Lawrence, KS
Fabrice Baijot , University of Kansas, Lawrence, KS
Erik Anderson , University of Kansas, Lawrence, KS
Jim Stevens , University of Kansas, Lawrence, KS
Jason Agron , University of Kansas, Lawrence, KS
pp. 89-98

A Type Architecture for Hybrid Micro-Parallel Computers (Abstract)

Brian Van Essen , University of Washington
Benjamin Ylvisaker , University of Washington
Carl Ebeling , University of Washington
pp. 99-110
Session 5: Multi-processor/Threaded System

A Scalable FPGA-based Multiprocessor (Abstract)

Arun Patel , University of Toronto, Toronto, ON, Canada
Manuel Saldana , University of Toronto, Toronto, ON, Canada
Christopher A. Madill , University of Toronto, Toronto, ON, Canada
Paul Chow , University of Toronto, Toronto, ON, Canada
Regis Pomes , University of Toronto, Toronto, ON, Canada
Christopher Comis , University of Toronto, Toronto, ON, Canada
pp. 111-120

A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism (Abstract)

Duncan A. Buell , The University of South Carolina
Jason D. Bakos , The University of South Carolina
Charles L. Cathey , The University of South Carolina
pp. 121-130

A Multithreaded Soft Processor for SoPC Area Reduction (Abstract)

Blair Fort , University of Toronto
Stephen D. Brown , University of Toronto
Davor Capalija , University of Toronto
Zvonko G. Vranesic , University of Toronto
pp. 131-142
Session 6: Graph Algorithms

GraphStep: A System Architecture for Sparse-Graph Algorithms (Abstract)

Thomas F. Jr. Knight , California Institute of Technology
Tomas E. Uribe , California Institute of Technology
Ian Eslick , California Institute of Technology
Andre DeHon , California Institute of Technology
Dominic Rizzo , California Institute of Technology
Michael deLorimier , California Institute of Technology
Raphael Rubin , California Institute of Technology
Nikil Mehta , California Institute of Technology
Nachiket Kapre , California Institute of Technology
pp. 143-151

Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths (Abstract)

Eric Stahlberg , Ohio Supercomputer Center, Columbus, OH
Pete Wyckoff , Ohio Supercomputer Center, Columbus, OH
P. Sadayappan , Ohio State University
James Dinan , Ohio State University
Joseph Fernando , Ohio Supercomputer Center, Springfield
Uday Bondhugula , Ohio State University
Ananth Devulapalli , Ohio Supercomputer Center, Springfield
pp. 152-164
Session 7: Power and Energy Optimization

A Field Programmable RFID Tag and Associated Design Flow (Abstract)

Marlin H. Mickle , University of Pittsburgh
Ralph Sprang , University of Pittsburgh
Raymond R. Hoare , University of Pittsburgh
Alex K. Jones , University of Pittsburgh
Swapna R. Dontharaju , University of Pittsburgh
James T. Cain , University of Pittsburgh
Josh Fazekas , University of Pittsburgh
Shenchih Tung , University of Pittsburgh
pp. 165-174

Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA (Abstract)

Wayne Luk , Imperial College London, UK
Oskar Mencer , Imperial College London, UK
Robert G. Dimond , Imperial College London, UK
pp. 175-184

Power Visualization, Analysis, and Optimization Tools for FPGAs (Abstract)

Li Wang , University of Southern California
Matthew French , University of Southern California
Michael Wirthlin , Brigham Young University
pp. 185-194
Session 8: Network Technology

Systematic Characterization of Programmable Packet Processing Pipelines (Abstract)

Gordon Brebner , Xilinx Research Labs, San Jose, USA
Michael Attig , Xilinx Research Labs, San Jose, USA
pp. 195-204

Packet Switched vs. Time Multiplexed FPGA Overlay Networks (Abstract)

Michael J. Wilson , California Institute of Technology
Michael Wrighton , California Institute of Technology
Henry Barnor , California Institute of Technology
Michael deLorimier , California Institute of Technology
Andre DeHon , California Institute of Technology
Raphael Rubin , California Institute of Technology
Nachiket Kapre , California Institute of Technology
Nikil Mehta , California Institute of Technology
pp. 205-216
Session 9: Biomedical and Cryptographic Applications

Single Pass, BLAST-Like, Approximate String Matching on FPGAs (Abstract)

Josh Model , Boston University; Boston, MA
Tom VanCourt , Boston University; Boston, MA
Bharat Sukhwani , Boston University; Boston, MA
Martin C. Herbordt , Boston University; Boston, MA
Yongfeng Gu , Boston University; Boston, MA
pp. 217-226

An FPGA Solution for Radiation Dose Calculation (Abstract)

Danny Z. Chen , University of Notre Dame
Kevin Whitton , University of Notre Dame
Cedric X. Yi , University of Maryland School of Medicine, Baltimore, MD
X. Sharon Hu , University of Notre Dame
pp. 227-236

A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2) (Abstract)

A. Bogdanov , Horst Gortz Institute for IT Security, Ruhr University Bochum, Germany
M.C. Mertens , Horst Gortz Institute for IT Security, Ruhr University Bochum, Germany
pp. 237-248
Session 10: Arithmetic

Advanced Components in the Variable Precision Floating-Point Library (Abstract)

Xiaojun Wang , Northeastern University, Boston, MA, USA
Miriam Leeser , Northeastern University, Boston, MA, USA
Sherman Braganza , Northeastern University, Boston, MA, USA
pp. 249-258
Posters

ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only Skills (Abstract)

Evgeny Fiksman , Israel Institute of Technology
Oskar Mencer , Imperial College, London, UK
Yitzhak Birk , Israel Institute of Technology
pp. 271-272

COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs (Abstract)

Oliver Diessel , University of New South Walesm, Australia
Shannon Koh , University of New South Walesm, Australia
pp. 273-274

A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design (Abstract)

Peter Y. K. Cheung , Imperial College London
George A. Constantinides , Imperial College London
Alastair M. Smith , Imperial College London
pp. 275-276

Defect-Tolerant Nanocomputing Using Bloom Filters (Abstract)

Wenrui Gong , University of California, Santa Barbara
Gang Wang , University of California, Santa Barbara
Ryan Kastner , University of California, Santa Barbara
pp. 277-278

A Programmable, Maximal Throughput Architecture for Neighborhood Image Processing (Abstract)

Reid Porter , Los Alamos National Lab, Los Alamos
Maya Gokhale , Los Alamos National Lab, Los Alamos
Christophe Wolinski , IRISA/IFSIC, France
Jan Frigo , Los Alamos National Lab, Los Alamos
Charles Wagner , IRISA/IFSIC, France
Francois Charot , IRISA/IFSIC, France
pp. 279-280

VPN Acceleration Using Reconfigurable System-On-Chip Technology (Abstract)

C. M. Wee , University of Queensland, Brisbane, QLD, 4072, Australia
J. A. Williams , University of Queensland, Brisbane, QLD, 4072, Australia
P. R. Sutton , University of Queensland, Brisbane, QLD, 4072, Australia
N. W. Bergmann , University of Queensland, Brisbane, QLD, 4072, Australia
pp. 281-282

An Optimized Finite Difference Computing Engine on FPGAs (Abstract)

Wei Zhao , Texas A&M University, College Station
Mi Lu , Texas A&M University, College Station
Guan Qin , Texas A&M University, College Station
Chuan He , Texas A&M University, College Station
pp. 283-284

Highly Efficient String Matching Circuit for IDS with FPGA (Abstract)

Kenji Toda , National Institute of Advanced Industrial Science and Technology
Yoshinori Yamaguchi , University of Tsukuba
Toshihiro Katashita , National Institute of Advanced Industrial Science and Technology, Japan
Atusi Maeda , University of Tsukuba
pp. 285-286

Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures (Abstract)

Manuel Jimenez , University of Puerto Rico, Mayaguez, PR
Domingo Rodriguez , University of Puerto Rico, Mayaguez, PR
Rafael Arce-Nazario , University of Puerto Rico, Mayaguez, PR
pp. 287-288

Scheduling divisible loads on partially reconfigurable hardware (Abstract)

K. N. Vikram , Indian Institute of Technology Madras, Chennai, India
V. Vasudevan , Indian Institute of Technology Madras, Chennai, India
pp. 289-290

General Architecture for Hardware Implementation of Genetic Algorithm (Abstract)

Keiichi Yasumoto , Nara Institute of Science and Technology
Tatsuhiro Tachibana , Nara Institute of Science and Technology
Naoki Shibata , Shiga University, Japan
Minoru Ito , Nara Institute of Science and Technology
Yoshihiro Murata , Nara Institute of Science and Technology
pp. 291-292

Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs (Abstract)

Warren J. Gross , McGill University, Canada
Yousef El-Kurdi , McGill University, Canada
Dennis Giannacopoulos , McGill University, Canada
pp. 293-294

Scalable Softcore Vector Processor for Biosequence Applications (Abstract)

Roger Chamberlain , Washington University in St. Louis
Arpith C. Jacob , Washington University in St. Louis
Brandon Harris , Washington University in St. Louis
Jeremy Buhler , Washington University in St. Louis
Young H. Cho , Washington University in St. Louis
pp. 295-296

Generating Parametrised Hardware Libraries from Higher-Order Descriptions (Abstract)

Oliver Pell , Imperial College, 180 Queen's, UK
Wayne Luk , Imperial College, 180 Queen's, UK
pp. 297-298

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM) (Abstract)

Ivan S. Kourtev, , University of Pittsburgh
Raymond Hoare , University of Pittsburgh
Alex K. Jones , University of Pittsburgh
pp. 299-300

Rapid Design of Special-Purpose Pipeline Processors with FPGAs and its Application to Computational Fluid Dynamics (Abstract)

Guillermo Marcus Martinez , University of Mannheim, B6-26B, D-68131 Mannheim, Germany
Reinhard Manner , University of Mannheim, B6-26B, D-68131 Mannheim, Germany
Andreas Kugel , University of Mannheim, B6-26B, D-68131 Mannheim, Germany
Gerhard Lienhart , University of Mannheim, B6-26B, D-68131 Mannheim, Germany
pp. 301-302

Floating-Point Accumulation Circuit for Matrix Applications (Abstract)

Michael R. Bodnar , University of Delaware
John R. Humphrey , EM Photonics, Inc.
James P. Durbano , EM Photonics, Inc.
Dennis W. Prather , University of Delaware
Petersen F. Curt , EM Photonics, Inc.
pp. 303-304

A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable Systems (Abstract)

Kyprianos Papademetriou , Technical University of Crete, Greece
Apostolos Dollas , Technical University of Crete, Greece
pp. 307-308

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture (Abstract)

Alex K. Jones , University of Pittsburgh
Gayatri Mehta , University of Pittsburgh
Raymond R. Hoare , University of Pittsburgh
Justin Stander , University of Pittsburgh
pp. 309-310

COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking (Abstract)

Sandeep Kumar , Ruhr University Bochum, Germany
Gerd Pfeiffer , Christian-Albrechts-University Kiel, Germany
Manfred Schimmler , Christian-Albrechts-University Kiel, Germany
Jan Pelzl , Ruhr University Bochum, Germany
Christof Paar , Ruhr University Bochum, Germany
pp. 311-312

FPGAs, GPUs and the PS2 - A Single Programming Methodology (Abstract)

Oskar Mencer , Imperial College London
Paul Price , Imperial College London
Lee W. Howes , Imperial College London
Olav Beckmann , Imperial College London
pp. 313-314

Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report (Abstract)

Yongfeng Gu , Boston University; Boston, MA
Tom VanCourt , Boston University; Boston, MA
Martin C. Herbordt , Boston University; Boston, MA
pp. 315-316

Parrotfish: Task Distribution in a Low Cost Autonomous ad hoc Sensor Network through Dynamic Runtime Reconfiguration (Abstract)

Dionissios Efstathiou , Technical University of Crete, Greece
Apostolos Dollas , Technical University of Crete, Greece
Konstantinos Kazakos , Technical University of Crete, Greece
pp. 319-320

Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital Devices (Abstract)

B Mc Ginley , National University of Ireland, Galway
F Morgan , National University of Ireland, Galway
J Maher , National University of Ireland, Galway
P Rocke , National University of Ireland, Galway
pp. 321-322

The STAR-C Truth: Analyzing Reconfigurable Supercomputing Reliability (Abstract)

Heather Quinn , Los Alamos National Laboratory, Los Alamos, NM
Maya Gokhale , Los Alamos National Laboratory, Los Alamos, NM
Paul Graham , Los Alamos National Laboratory, Los Alamos, NM
Christof Teuscher , Los Alamos National Laboratory, Los Alamos, NM
Debayan Bhaduri , Los Alamos National Laboratory, Los Alamos, NM
pp. 323-324

Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs (Abstract)

S. Mondal , University, Evanston, IL
S. O. Memik , University, Evanston, IL
N. Bellas , University, Evanston, IL
pp. 325-326

Hierarchical Clustering using Reconfigurable Devices (Abstract)

John Lockwood , Washington University in St. Louis
Young Cho , Washington University in St. Louis
Dan Legorreta , Washington University in St. Louis
Moshe Looks , Washington University in St. Louis
Shobana Padmanabhan , Washington University in St. Louis
pp. 327-328

CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures (Abstract)

S. Dai , University of California, Irvine
E. Bozorgzadeh , University of California, Irvine
pp. 329-330

A Scalable Architecture for RSA Cryptography on Large FPGAs (Abstract)

Duncan Buell , University of South Carolina
Allen Michalski , University of South Carolina
pp. 331-332

Design of a Reconfigurable Processor for NIST Prime Field ECC (Abstract)

Kendall Ananyi , University of Victoria, Canada
Daler Rakhmatov , University of Victoria, Canada
pp. 333-334

Switch Box Architectures for Three-Dimensional FPGAs (Abstract)

Arif Rahman , Xilinx Research Labs
Mahmut Kandemir , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
Aman Gayasen , Pennsylvania State University
pp. 335-336

A Scalable Hybrid Regular Expression Pattern Matcher (Abstract)

James Moscola , Washington University, St. Louis, Missouri
John W. Lockwood , Washington University, St. Louis, Missouri
Young H. Cho , Washington University, St. Louis, Missouri
pp. 337-338

Hardware/Software Co-Design Architecture for Lattice Decoding Algorithms (Abstract)

Jing Ma , University of New Orleans, New Orleans, LA
Cao Liang , University of New Orleans, New Orleans, LA
Xinming Huang , University of New Orleans, New Orleans, LA
pp. 339-340

High Performance Feature Detection on a Reconfigurable Co-Processor (Abstract)

Alessandro Bissacco , University of California at Los Angeles
Soheil Ghiasi , University of California at Davis
Jia Ming Mar , University of California at Davis
Stefano Soatto , University of California at Los Angeles
pp. 341-342

DSynth: A Pipeline Synthesis Environment for FPGAs (Abstract)

Welson Sun , Brigham Young University, Provo, UT
Michael Wirthlin , Brigham Young University, Provo, UT
pp. 343-344

Template-Based Generation of Streaming Accelators from a High Level Presentation (Abstract)

Sek M. Chai , Embedded Systems Research, Motorola Inc.
Malcolm Dwyer , Embedded Systems Research, Motorola Inc.
Nikolaos Bellas , Embedded Systems Research, Motorola Inc.,
Dan Linzmeier , Embedded Systems Research, Motorola Inc.
pp. 345-346

Scalable Hardware Architecture for Real-Time Dynamic Programming Applications (Abstract)

Itamar Elhanany , University of Tennessee at Knoxville
Brad Matthews , University of Tennessee at Knoxville
pp. 347-348

Open Source High Performance Floating-Point Modules (Abstract)

Keith D. Underwood , Sandia National Laboratories
K. Scott Hemmert , Sandia National Laboratories
pp. 349-350

A Reconfigurable Cluster-on-Chip Architecture with MPI Communication Layer (Abstract)

J. Wu , University of Queensland, Brisbane, Australia
J.A. Williams , University of Queensland, Brisbane, Australia
I. Syed , University of Queensland, Brisbane, Australia
N.W. Bergmann , University of Queensland, Brisbane, Australia
pp. 351-352
Author Index

Author Index (PDF)

pp. 353
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