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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2005)
Los Alamitos
Apr. 18, 2005 to Apr. 20, 2005
ISBN: 0-7695-2445-1
TABLE OF CONTENTS
Introduction
Session 1: Applications 1

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Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs (Abstract)

Zachary K. Baker , University of Southern California
Viktor K. Prasanna , University of Southern California
pp. 3-12

A Novel 2D Filter Design Methodology for Heterogeneous Devices (Abstract)

George A. Constantinides , Imperial College London
Peter Y. K. Cheung , Imperial College London
Christos-Savvas Bouganis , Imperial College London
pp. 13-22

Prototyping Architectural Support for Program Rollback Using FPGAs (Abstract)

Radu Teodorescu , University of Illinois at Urbana-Champaign
Josep Torrellas , University of Illinois at Urbana-Champaign
pp. 23-32
Session 2: Architecture

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Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture (Abstract)

Steven J. E. Wilton , University of British Columbia
Zion Kwok , University of British Columbia
pp. 35-44
Session 3: Tools 1

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A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation (Abstract)

Frank Vahid , University of California at Riverside
Sheldon X.-D. Tan , University of California at Riverside
Roman Lysecky , University of California at Riverside
pp. 57-62
Session 4: Graphics

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FPGA Particle Graphics Hardware (Abstract)

Warren J. Gross , McGill University
John Sachs Beeckler , McGill University
pp. 85-94

Reconfigurable Designs for Radiosity (Abstract)

Tim Todman , Imperial College
Henry Styles , Imperial College
Paul Baker , Imperial College
Wayne Luk , Imperial College
pp. 95-104
Session 5: Applications 2

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Hardware Factorization Based on Elliptic Curve Method (Abstract)

Colin Stahlke , EDIZONE GmbH
Jens Franke , University of Bonn
Martin Šimka , Technical University of Košice
Jan Pelzl , Ruhr University Bochum
Miloš Drutarovský , Technical University of Košice
Christine Priplata , EDIZONE GmbH
Thorsten Kleinjung , University of Bonn
Viktor Fischer , Université Jean Monnet
pp. 107-116

Metropolitan Road Traffic Simulation on FPGAs (Abstract)

Maya Gokhale , Los Alamos National Laboratory
Anders Å. Hansson , Los Alamos National Laboratory
Henning S. Mortveit , Los Alamos National Laboratory
Justin L. Tripp , Los Alamos National Laboratory
pp. 117-126

Time Domain Numerical Simulation for Transient Waves on Reconfigurable Coprocessor Platform (Abstract)

Chuan He , Texas A&M University
Wei Zhao , Texas A&M University
Mi Lu , Texas A&M University
pp. 127-136
Session 6: Run Time

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An Execution Environment for Reconfigurable Computing (Abstract)

Katherine Compton , University of Wisconsin at Madison
Wenyin Fu , University of Wisconsin at Madison
pp. 149-158
Session 7: Arithmetic

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Higher Radix Floating-Point Representations for FPGA-Based Arithmetic (Abstract)

Brent Nelson , Brigham Young University
Bryan Catanzaro , Brigham Young University
pp. 161-170

An Analysis of the Double-Precision Floating-Point FFT on FPGAs (Abstract)

K. Scott Hemmert , Sandia National Laboratories
Keith D. Underwood , Sandia National Laboratories
pp. 171-180

A Comparison of Floating Point and Logarithmic Number Systems for FPGAs (Abstract)

K. Scott Hemmert , Sandia National Labratories
Michael Haselman , University of Washington
Michael Beauchamp , University of Washington
Scott Hauck , University of Washington
Keith Underwood , Sandia National Labratories
Aaron Wood , University of Washington
pp. 181-190
Session 8: Device Architecture

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Terrestrial-Based Radiation Upsets: A Cautionary Tale (Abstract)

Heather Quinn , Los Alamos National Laboratory
Paul Graham , Los Alamos National Laboratory
pp. 193-202

Automating the Layout of Reconfigurable Subsystems Using Circuit Generators (Abstract)

Shawn Phillips , University of Washington
Scott Hauck , University of Washington
pp. 203-212
Session 9: Networking

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Fast Reconfiguring Deep Packet Filter for 1+ Gigabit Network (Abstract)

William H. Mangione-Smith , University of California at Los Angeles
Young H. Cho , University of California at Los Angeles
pp. 215-224

A Framework for Rule Processing in Reconfigurable Network Systems (Abstract)

John Lockwood , Washington University in Saint Louis
Michael Attig , Washington University in Saint Louis
pp. 225-234

A Signature Match Processor Architecture for Network Intrusion Detection (Abstract)

Janardhan Singaraju , University of Connecticut
Long Bu , University of Connecticut
John A. Chandy , University of Connecticut
pp. 235-242
Session 10: Tools 2

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Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation (Abstract)

Jun Jiang , Imperial College London
José Gabriel F. Coutinho , Imperial College London
Wayne Luk , Imperial College London
pp. 245-254
Posters

A BIST Approach for Testing FPGAs Using JBITS (PDF)

Surya S. Hejeebu , University of Toledo
M. Alam , University of Toledo
M. Y. Niamat , University of Toledo
pp. 267-268

Preliminary Report: FPGA Acceleration of Molecular Dynamics Computations (PDF)

Yongfeng Gu , Boston University
Tom Van Court , Boston University
Martin C. Herbordt , Boston University
Douglas DiSabello , Boston University
pp. 269-270

A High-Performance Asynchronous FPGA: Test Results (PDF)

John Teifel , Cornell University
Rajit Manohar , Cornell University
David Fang , Cornell University
pp. 271-272

Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures (PDF)

Sudarshan Banerjee , University of California at Irvine
Nikil Dutt , University of California at Irvine
Elaheh Bozorgzadeh , University of California at Irvine
pp. 273-274

RAVIOLI — Reconfigurable Arithmetic Variable-Precision Implementations of On-Line Instructions (PDF)

Miloš D. Ercegovac , Univesity of California at Los Angeles
Robert McIlhenny , California State University at Northridge
pp. 275-276

FIFO Communication Models in Operating Systems for Reconfigurable Computing (PDF)

J. A. Williams , University of Queensland
X. Xie , University of Queensland
N. W. Bergmann , University of Queensland
pp. 277-278

Astrophysical Hydrodynamics Simulations on a Reconfigurable System (PDF)

Tsuyoshi Hamada , Institute of Physical and Chemical Research
Naohito Nakasato , Institute of Physical and Chemical Research
pp. 279-280
Posters

FPGA-Based CDMA Switch for Networks-on-Chip (PDF)

Daewook Kim , University of Minnesota
Manho Kim , University of Minnesota
Gerald E. Sobelman , University of Minnesota
pp. 283-284

Design of Networked Reconfigurable Encryption Engine (PDF)

Ha Yajun , National University of Singapore
Shakith Fernando , National University of Singapore
pp. 285-286

A Virtual Machine for Merit-Based Runtime Reconfiguration (PDF)

Ron Sass , University of Kansas
Brian Greskamp , University of Illinois at Urbana-Champaign
pp. 287-288
Posters

The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture (PDF)

Xin Jia , University of Cincinnati
Ranga Vemuri , University of Cincinnati
pp. 291-292

Optimizing Technology Mapping for FPGAs Using CAMs (PDF)

Joshua M. Lucas , University of Pittsburgh
Alex K. Jones , University of Pittsburgh
Raymond Hoare , University of Pittsburgh
pp. 293-294

An Architecture for Video Compression Based on the SCAN Algorithm (PDF)

A. Dollas , Technical University of Crete
H. Sofikitis , Technical University of Crete
K. Roumpou , Technical University of Crete
N. Bourbakis , Wright State University
pp. 295-296

An Open TCP/IP Core for Reconfigurable Logic (PDF)

Ioannis Zisis , Technical University of Crete
Apostolos Dollas , Technical University of Crete
Ioannis Ermis , Technical University of Crete
Christopher Kachris , Technical University of Crete
Iosif Koidis , Technical University of Crete
pp. 297-298

Mutable Codesign for Embedded Protocol Processing (PDF)

Gordon Brebner , Xilinx, Inc.
Christopher Neely , Xilinx, Inc.
Todd Sproull , Washington University in Saint Louis
pp. 299-300

An Embedded Reconfigurable Datapath for SoC (PDF)

Mario Toma , STMicroelectronics
Andrea Lodi , University of Bologna
Luca Ciccarelli , University of Bologna
Claudio Mucci , University of Bologna
Roberto Giansante , University of Bologna
Andrea Cappelli , University of Bologna
pp. 303-304

Hardware Solution to Java Compressed Heap (PDF)

Chia-Tien Dan Lo , University of Texas at San Antonio
Mayumi Kato , University of Texas at San Antonio
pp. 307-308

A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms (PDF)

Fernando E. Ortiz , EM Photonics, Inc.
John R. Humphrey , EM Photonics, Inc.
Petersen F. Curt , EM Photonics, Inc.
James P. Durbano , EM Photonics, Inc.
Dennis W. Prather , University of Delaware
pp. 309-310

Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA (Abstract)

Reza Rastegar , Amirkabir University of Technology
Morteza Saheb Zamani , Amirkabir University of Technology
Mohammad R. Meybodi , Amirkabir University of Technology
Arash Hariri , Amirkabir University of Technology
pp. 311-314

A System-on-Programmable Chip Approach for MIMO Sphere Decoder (PDF)

Jing Ma , University of New Orleans
Xinming Huang , University of New Orleans
pp. 317-318

The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform (PDF)

Jan van der Veen , Braunschweig University of Technology
Thomas Haller , University of Erlangen-Nuremberg
Ali Ahmadinia , University of Erlangen-Nuremberg
Mateusz Majer , University of Erlangen-Nuremberg
Jürgen Teich , Braunschweig University of Technology
André Linarth , University of Erlangen-Nuremberg
Christophe Bobda , University of Erlangen-Nuremberg
pp. 319-320

Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms (PDF)

Marco D. Santambrogio , Politecnico di Milano
Fabrizio Ferrandi , Politecnico di Milano
Alberto Donato , Politecnico di Milano
Massimo Redaelli , Politecnico di Milano
Donatella Sciuto , Politecnico di Milano
pp. 321-322

High-Performance FPGA-Based General Reduction Methods (PDF)

Viktor K. Prasanna , University of Southern California
Ling Zhuo , University of Southern California
Gerald R. Morris , University of Southern California
pp. 323-324

The DARPA Dynamic Programming Benchmark on a Reconfigurable Computer. (PDF)

Sreesa Akella , University of South Carolina
Duncan A. Buell , University of South Carolina
Luis E. Cordova , University of South Carolina
pp. 327-328

Massively Parallel Processors Generator for Reconfigurable System (PDF)

Tsuyoshi Hamada , Institute of Physical and Chemical Research
Naohito Nakasato , Institute of Physical and Chemical Research
pp. 329-330

FPGA-Based Vector Processing for Solving Sparse Sets of Equations (PDF)

Muhammad Z. Hasan , New Jersey Institute of Technology
Sotirios G. Ziavras , New Jersey Institute of Technology
pp. 331-332

Exploiting Multi-Grained Parallelism in Reconfigurable SBC Architectures (PDF)

Joseph Zambreno , Northwestern University
Alok Choudhary , Northwestern University
Dan Honbo , Northwestern University
pp. 333-334

On Distributed Reconfigurable Systems: Open Problems and Some Initial Solutions (PDF)

Georgios Vernardos , Technical University of Crete
Dionissios Efstathiou , Technical University of Crete
Elias Polytarchos , Technical University of Crete
Apostolos Dollas , Technical University of Crete
Konstantinos Kazakos , Technical University of Crete
pp. 335-336
Author Index

Author Index (PDF)

pp. 337-338
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