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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2004)
Napa, California
Apr. 20, 2004 to Apr. 23, 2004
ISBN: 0-7695-2230-0
TABLE OF CONTENTS
Session 1: Architecture

Time-Critical Software Deceleration in an FCCM (Abstract)

Dennis Bemmann , Humboldt University, Berlin, Germany
Gordon Brebner , Xilinx Research Labs, San Jose, CA, USA
Phil James-Roxby , Xilinx Research Labs, Longmont, CO, USA
pp. 3-12

Design Patterns for Reconfigurable Computing (Abstract)

Andr? DeHon , California Institute of Technology, Pasadena, CA
Michael Vanier , California Institute of Technology, Pasadena, CA
Michael DeLorimier , California Institute of Technology, Pasadena, CA
Helia Naeimi , California Institute of Technology, Pasadena, CA
Yuki Matsuda , California Institute of Technology, Pasadena, CA
Nachiket Kapre , California Institute of Technology, Pasadena, CA
Joshua Adams , California Institute of Technology, Pasadena, CA
Michael Wrighton , California Institute of Technology, Pasadena, CA
pp. 13-23

Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor (Abstract)

Paolo Ienne , Swiss Federal Institute of Technology Lausanne, Switzerland
Miljan Vuletic , Swiss Federal Institute of Technology Lausanne, Switzerland
Laura Pozzi , Swiss Federal Institute of Technology Lausanne, Switzerland
pp. 24-33
Session 2: Tools I

Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs (Abstract)

David Zaretsky , Northwestern University, Evanston, IL
Xiaoyong Tang , Northwestern University, Evanston, IL
Prith Banerjee , Northwestern University, Evanston, IL
Gaurav Mittal , Northwestern University, Evanston, IL
pp. 37-46

PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAs (Abstract)

Jingzhao Ou , University of Southern California, Los Angeles
Viktor K. Prasanna , University of Southern California, Los Angeles
pp. 47-56
Session 3: Arithmetic I

Automated Least-Significant Bit Datapath Optimization for FPGAs (Abstract)

Scott Hauck , University of Washington, Seattle
Mark L. Chang , University of Washington, Seattle
pp. 59-67

An Arithmetic Library and Its Application to the N-body Problem (Abstract)

H. C. Yeung , The Chinese University of Hong Kong
P. H. W. Leong , The Chinese University of Hong Kong
C. H. Ho , The Chinese University of Hong Kong
K. H. Tsoi , The Chinese University of Hong Kong
pp. 68-78

Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs (Abstract)

Wayne Luk , Imperial College, London, UK
Oskar Mencer , Imperial College, London, UK
Peter Y. K. Cheung , Imperial College, London, UK
Altaf Abdul Gaffar , Imperial College, London, UK
pp. 79-88
Session 4: Communications Applications

A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder (Abstract)

Dennis Goeckel , University of Massachusetts, Amherst, MA
Russell Tessier , University of Massachusetts, Amherst, MA
Jian Liang , University of Massachusetts, Amherst, MA
pp. 91-100

A Flexible Hardware Encoder for Low-Density Parity-Check Codes (Abstract)

Dong-U Lee , Imperial College, London, UK
Wayne Luk , Imperial College, London, UK
John Villasenor , University of California, Los Angeles, USA
Christopher Jones , University of California, Los Angeles, USA
Connie Wang , University of California, Los Angeles, USA
Michael Smith , University of California, Los Angeles, USA
pp. 101-111
Session 5: Networking I

ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers (Abstract)

Raj Krishnamurthy , IBM Research Zurich Labs, Switzerland
Karsten Schwan , Georgia Institute of Technology, Atlanta, GA
Richard West , Georgia Institute of Technology, Atlanta, GA
Sudhakar Yalamanchili , Georgia Institute of Technology, Atlanta, GA
pp. 115-124

Deep Packet Filter with Dedicated Logic and Read Only Memories (Abstract)

William H. Mangione-Smith , University of California, Los Angeles
Young H. Cho , University of California, Los Angeles
pp. 125-134

A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs (Abstract)

Viktor K. Prasanna , University of Southern California, Los Angeles
Zachary K. Baker , University of Southern California, Los Angeles
pp. 135-144
Session 6: Applications I

Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications (Abstract)

Miriam Leeser , Northeastern University, Boston, MA
Shawn Miller , Northeastern University, Boston, MA
Haiqian Yu , Northeastern University, Boston, MA
pp. 147-155

FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain Method (Abstract)

Petersen F. Curt , University of Delaware
Dennis W. Prather , University of Delaware
James P. Durbano , EM Photonics, Inc.
Fernando E. Ortiz , University of Delaware
John R. Humphrey , University of Delaware
pp. 156-163
Session 7: Tools II

Register Binding for FPGAs with Embedded Memory (Abstract)

Hassan Al Atat , Lebanese American University, Byblos, Lebanon
Iyad Ouaiss , Lebanese American University, Byblos, Lebanon
pp. 167-175

Defect and Fault Tolerance of Reconfigurable Molecular Computing (Abstract)

Subhasish Mitra , Intel Corporation, Sacramento, CA
Mehdi B. Tahoori , Northeastern University, Boston, MA
pp. 176-185

Communications Scheduling for Concurrent Processes on Reconfigurable Computers (Abstract)

Janette Frigo , Los Alamos National Laboratory, Los Alamos, NM
Christophe Wolinski , IRISA, IFSIC France
Christine Ahrens , Los Alamos National Laboratory, Los Alamos, NM
Maya Gokhale , Los Alamos National Laboratory, Los Alamos, NM
pp. 186-193
Session 8: Applications II

Reconfigurable Molecular Dynamics Simulator (Abstract)

Ian Kuon , University of Toronto, Ontario, Canada
Paul Chow , University of Toronto, Ontario, Canada
Navid Azizi , University of Toronto, Ontario, Canada
Aaron Egier , University of Toronto, Ontario, Canada
Ahmad Darabiha , University of Toronto, Ontario, Canada
pp. 197-206

Accelerating Seismic Migration Using FPGA-Based Coprocessor Platform (Abstract)

Chuanwen Sun , Texas A&M University, College Station, TX
Mi Lu , Texas A&M University, College Station, TX
Chuan He , Texas A&M University, College Station, TX
pp. 207-216
Session 9: Arithmetic II

Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance (Abstract)

K. Scott Hemmert , Sandia National Laboratories, Albuquerque, NM
Keith D. Underwood , Sandia National Laboratories, Albuquerque, NM
pp. 219-228

FPGA-Based Implementation of a Robust IEEE-754 Exponential Unit (Abstract)

Christopher C. Doss , North Carolina A & T State University, Greensboro, NC
Robert L. Riley, Jr. , Air Force Research Laboratory, Eglin AFB, FL
pp. 229-238

Design of an On-Line IEEE Floating-Point Addition Unit for FPGAs (Abstract)

Steven D. Krueger , Texas Instruments, Inc., Dallas, TX
Peter-Michael Seidel , Southern Methodist University, Dallas, TX
pp. 239-246
Session 10: Networking II

Scalable Pattern Matching for High Speed Networks (Abstract)

Christopher R. Clark , Georgia Institute of Technology, Atlanta, GA
David E. Schimmel , Georgia Institute of Technology, Atlanta, GA
pp. 249-257

Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern Matching (Abstract)

Ioannis Sourdis , Technical University of Crete, Chania, Greece
Dionisios Pnevmatikatos , Foundation for Research and Technology-Hellas (FORTH), Greece
pp. 258-267
Posters

A Structured System Methodology for FPGA Based System-on-A-Chip Design (PDF)

George Constantinides , Imperial College, UK
Pete Sedcole , Imperial College, UK
Wayne Luk , Imperial College, UK
Peter Y. K. Cheung , Imperial College, UK
pp. 271-272

Fine-Tuning Loop-Level Parallelism for Increasing Performance of DSP Applications on FPGAs (PDF)

Andy P. Nisbet , Trinity College, Dublin, Ireland
Emre ?zre , Trinity College, Dublin, Ireland
David Gregg , Trinity College, Dublin, Ireland
pp. 273-274

Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path (PDF)

S. Tragoudas , Southern Illinois University, USA
C. E. Goutis , University of Patras, Greece
M. D. Galanis , University of Patras, Greece
D. Soudris , Democritus University, Greece
G. Theodoridis , Aristotle University, Greece
pp. 275-276

Hardware-in-the-Loop Evolution of a 3-bit Multiplier (PDF)

Jason D. Lohn , NASA Ames Research Center, Moffett Field, CA
Gregory V. Larchev , NASA Ames Research Center, Moffett Field, CA
pp. 277-278

FPGA Montgomery Multiplier Architectures - A Comparison (Abstract)

M?ire McLoone , Queen's University of Belfast, Northern Ireland
Ciaran McIvor , Queen's University of Belfast, Northern Ireland
John V. McCanny , Queen's University of Belfast, Northern Ireland
pp. 279-282

Design Methodology of a Configurable System-on-Chip Architecture (PDF)

Sebastian Wallner , Technical University Hamburg-Harburg, Germany
pp. 283-284

Word-Length Optimization of Folded Polynomial Evaluation (PDF)

George A. Constantinides , Imperial College London
Nalin Sidahao , Imperial College London
Abunaser Miah , Imperial College London
pp. 285-286

Migrating Functionality from ROMS to Embedded Multipliers (PDF)

George A. Constantinides , Imperial College, London
Peter Y. K. Cheung , Imperial College, London
Gareth W. Morris , Imperial College, London
pp. 287-288

A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation (PDF)

Anant Agarwal , MIT Computer Science and Artificial Intelligence Laboratory
David Wentzlaff , MIT Computer Science and Artificial Intelligence Laboratory
pp. 289-290

Validation of an Advanced Encryption Standard (AES) IP Core (PDF)

Valeri Tomashau , Algotronix Ltd., Edinburgh, UK
Tom Kean , Algotronix Ltd., Edinburgh, UK
pp. 291-292

Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays (Abstract)

Sami Khawam , The University of Edinburgh, UK
Fred Westall , EPSON Scotland Design Centre, Livingston, UK
Tughrul Arslan , The Alba Centre, Livingston, UK
pp. 293-295

The MOLEN Processor Prototype (Abstract)

Georgi Gaydadjiev , EEMCS, TU Delft, The Netherlands
Georgi Kuzmanov , EEMCS, TU Delft, The Netherlands
Stamatis Vassiliadis , EEMCS, TU Delft, The Netherlands
pp. 296-299

FPGA Acceleration of Rigid Molecule Interactions (PDF)

Yongfeng Gu , Boston University, MA
Tom Van Court , Boston University, MA
Martin C. Herbordt , Boston University, MA
pp. 300-301

A Single Program Multiple Data Parallel Processing Platform for FPGAs (PDF)

Phil James-Roxby , Xilinx Research Labs, Longmont, CO, USA
Charlie Ross , Colorado State University, Fort Collins, CO, USA
Paul Schumacher , Xilinx Research Labs, Longmont, CO, USA
pp. 302-303

Hyperreconfigurable Architectures for Fast Run Time Reconfiguration (PDF)

Sebastian Lange , University of Leipzig, Germany
Martin Middendorf , University of Leipzig, Germany
pp. 304-305

A Generator of High-Speed Floating-Point Modules (PDF)

Octavio Nieto-Taladriz , Universidad Polit?cnica de Madrid, Spain
Carlos Carreras , Universidad Polit?cnica de Madrid, Spain
Gabriel Caffarena , Universidad Polit?cnica de Madrid, Spain
Gerardo Leyva , Universidad Polit?cnica de Madrid, Spain
pp. 306-307

A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA (PDF)

Alireza Hodjat , University of California, Los Angeles
Ingrid Verbauwhede , University of California, Los Angeles
pp. 308-309

An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding (PDF)

Warren J. Gross , McGill University, Montreal, Canada
Frank R. Kschischang , University of Toronto, Canada
P. Glenn Gulak , University of Toronto, Canada
pp. 310-311

Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems (Abstract)

Andreas Herkersdorf , Institute for Integrated Systems/TUM, Germany
Helmut Steckenbiller , Fraunhofer Institute for Communication Systems, Germany
Dirk Eilers , Fraunhofer Institute for Communication Systems, Germany
pp. 312-315

FPGA Based Network Intrusion Detection using Content Addressable Memories (PDF)

John A. Chandy , University of Connecticut, Storrs, CT
Long Bu , University of Connecticut, Storrs, CT
pp. 316-317

Using FIFOs in Hardware-Software Co-Design for FPGA Based Embedded Systems (PDF)

Wim Bohm , Colorado State University, Ft. Collins
Charlie Ross , Colorado State University, Ft. Collins
pp. 318-319

A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing (PDF)

Jianchun Li , Case Western Reserve University, Cleveland, OH
Christos Papachristou , Case Western Reserve University, Cleveland, OH
Raj Shekhar , Cleveland Clinic Foundation, Cleveland, OH
pp. 320-321

Implementation Results of Bloom Filters for String Matching (PDF)

Michael Attig , Washington University, St. Louis, MO
John Lockwood , Washington University, St. Louis, MO
Sarang Dharmapurikar , Washington University, St. Louis, MO
pp. 322-323

An FPGA Implementation for a High Throughput Adaptive Filter Using Distributed Arithmetic (PDF)

Heejong Yoo , Georgia Institute of Technology, Atlanta, GA
Walter Huang , Georgia Institute of Technology, Atlanta, GA
Venkatesh Krishnan , Georgia Institute of Technology, Atlanta, GA
Daniel J. Allred , Georgia Institute of Technology, Atlanta, GA
David V. Anderson , Georgia Institute of Technology, Atlanta, GA
pp. 324-325

Power Management for FPGAs: Power-Driven Design Partitioning (PDF)

Seda Ogrenci Memik , Northwestern University
Rajarshi Mukherjee , Northwestern University
pp. 326-327

Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor (PDF)

Kazutoshi Wakabayashi , NEC System Devices Research Lab., Japan
Masayasu Suzuki , Keio University, Japan
Yohei Hasegawa , Keio University, Japan
Kenichiro Anjo , NEC Electronics, Japan
Takeo Toi , NEC System Devices Research Lab., Japan
Toru Awashima , NEC System Devices Research Lab., Japan
Noriaki Suzuki , Keio University, Japan
Naoto Kaneko , Keio University, Japan
Katsuaki Deguchi , Keio University, Japan
Shunsuke Kurotaki , Keio University, Japan
Yutaka Yamada , Keio University, Japan
Hideharu Amano , Keio University, Japan
Masato Motomura , NEC Electronics, Japan
pp. 328-329

FPGA based Embedded Processing Architecture for the QRD-RLS Algorithm (PDF)

Deepak Boppana , Altera Corporation, San Jose, CA
Kully Dhanoa , Altera Corporation, San Jose, CA
Jesse Kempa , Altera Corporation, San Jose, CA
pp. 330-331

A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow (PDF)

Claudio Mucci , ARCES - University of Bologna, Bologna, Italy
Andrea Cappelli , ARCES - University of Bologna, Bologna, Italy
Fabio Campi , ARCES - University of Bologna, Bologna, Italy
Andrea Lodi , ARCES - University of Bologna, Bologna, Italy
Mario Toma , ARCES - University of Bologna, Bologna, Italy
pp. 332-333

Secure Remote Control of Field-programmable Network Devices (PDF)

Jing Lu , Washington University in St. Louis, USA
Haoyu Song , Washington University in St. Louis, USA
James Moscola , Washington University in St. Louis, USA
John Lockwood , Washington University in St. Louis, USA
pp. 334-335

An Alternate Wire Database for Xilinx FPGAs (PDF)

Peter Athanas , Virginia Polytechnic Institute and State University, Blacksburg, VA
Neil Steiner , Virginia Polytechnic Institute and State University, Blacksburg, VA
pp. 336-337

Duty Cycle Aware Application Design using FPGAs (PDF)

Sumit Mohanty , University of Southern California, Los Angeles
Viktor K. Prasanna , University of Southern California, Los Angeles
pp. 338-339

Automating the Layout of Reconfigurable Subsystems Via Template Reduction (PDF)

Shawn Phillips , University of Washington, Seattle, WA
Scott Hauck , University of Washington, Seattle, WA
Akshay Sharma , University of Washington, Seattle, WA
pp. 340-341

Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine (Abstract)

Lothar Thiele , Swiss Federal Institute of Technology (ETH) Zurich, Switzerland
Marco Platzner , Swiss Federal Institute of Technology (ETH) Zurich, Switzerland
Matthias Dyer , Swiss Federal Institute of Technology (ETH) Zurich, Switzerland
pp. 342-344

Author Index (PDF)

pp. 345-346
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