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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2003)
Napa, California
Apr. 9, 2003 to Apr. 11, 2003
ISSN: 1082-3409
ISBN: 0-7695-1979-2
TABLE OF CONTENTS
Session 1: Applications

A High I/O Reconfigurable Crossbar Switch (Abstract)

Steve Young , Xilinx Inc
Scott McMillan , Xilinx Inc
Colm Fewer , Xilinx Ireland
Peter Alfke , Xilinx Inc
Delon Levi , Xilinx Inc
Brandon Blodget , Xilinx Inc
pp. 3

Congruential Sieves on a Reconfigurable Computer (Abstract)

Duncan A. Buell , University of South Carolina
Heather A. Wake , University of South Carolina
pp. 11
Session 2: Network Security

Implementation of a Content-Scanning Module for an Internet Firewall (Abstract)

John Lockwood , Washington University, St. Louis, MO
James Moscola , Washington University, St. Louis, MO
Ronald P. Loui , Washington University, St. Louis, MO
Michael Pachos , Washington University, St. Louis, MO
pp. 31

Compiling Policy Descriptions into Reconfigurable Firewall Processors (Abstract)

N. Dulay , Imperial College
W. Luk , Imperial College
T.K. Lee , Imperial College
E. Lupu , Imperial College
M. Sloman , Imperial College
S. Yusuf , Imperial College
pp. 39
Session 3: Communication Techniques

Compact FPGA-based True and Pseudo Random Number Generators (Abstract)

P.H.W. Leong , The Chinese University of Hong Kong
K.H. Tsoi , The Chinese University of Hong Kong
K.H. Leung , The Chinese University of Hong Kong
pp. 51

Accelerating Bit Error Rate Testing Using a System Level Design Tool (Abstract)

J. Hwang , Xilinx Inc.
V. Singh , Xilinx Inc.
A. Root , Xilinx Inc.
E. Hemphill , Xilinx Inc.
N. Shirazi , Xilinx Inc.
pp. 62

A Hardware Gaussian Noise Generator for Channel Code Evaluation (Abstract)

Peter Y.K. Cheung , Imperial College London
John Villasenor , University of California Los Angeles
Wayne Luk , Imperial College London
Dong-U Lee , Imperial College London
pp. 69
Session 4: Arithmetic

Improved Small Multiplier Based Multiplication, Squaring and Division (Abstract)

N. Burgess , Cardiff University
B.R. Lee , Cardiff University
pp. 91
Session 5: Device Architecture

Issues and Approaches to Coarse-Grain Reconfigurable Architecture Development (Abstract)

Ken Eguro , University of Washington, Seattle
Scott Hauck , University of Washington, Seattle
pp. 111

Asynchronous PipeRench: Architecture and Performance Estimations (Abstract)

Herman Schmit , Carnegie Mellon University
Hiroto Kagotani , Okayama University
pp. 121
Session 6: Fault Modeling and Recovery

The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets (Abstract)

Paul Graham , Los Alamos National Laboratory, Los Alamos, NM
Michael Wirthlin , Brigham Young University, Provo, UT
Eric Johnson , Brigham Young University, Provo, UT
Michael Caffrey , Los Alamos National Laboratory, Los Alamos, NM
Nathan Rollins , Brigham Young University, Provo, UT
pp. 133

Adaptive Fault Recovery for Networked Reconfigurable Systems (Abstract)

Ramshankar Ramanarayanan , University of Massachusetts
Russell Tessier , University of Massachusetts
Weifeng Xu , University of Massachusetts
pp. 143
Session 7: Applications

Gamma-Ray Pulsar Detection using Reconfigurable Computing Hardware (Abstract)

David Palmer , Los Alamos National Laboratory
Marc Popkin-Paine , Los Alamos National Laboratory
Maya Gokhale , Los Alamos National Laboratory
Jan Frigo , Los Alamos National Laboratory
pp. 155

Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA (Abstract)

D. Crookes , The Queen?s University of Belfast
K Benkrid , The Queen?s University of Belfast
A Benkrid , The Queen?s University of Belfast
pp. 162

Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines (Abstract)

Miriam Leeser , Northeastern University
L.A. Smith King , College of the Holy Cross
Waleed Meleis , Northeastern University
Heather Quinn , Northeastern University
pp. 173
Session 8: Arithmetic

Floating Point Unit Generation and Evaluation for FPGAs (Abstract)

Russell Tessier , University of Massachusetts
Jian Liang , University of Massachusetts
Oskar Mencer , Imperial College
pp. 185
Session 9: Programming Frameworks

Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures (Abstract)

Joonseok Park , University of Southern California
Pedro C. Diniz , University of Southern California
pp. 207

Simulation and Synthesis of CSP-based Interprocess Communication (Abstract)

Justin L. Tripp , Brigham Young University
Preston A. Jackson , Brigham Young University
Brad L. Hutchings , Brigham Young University
pp. 218

Source Level Debugger for the Sea Cucumber Synthesizing Compiler (Abstract)

K. Scott Hemmert , Brigham Young University
Brad L. Hutchings , Brigham Young University
Justin L. Tripp , Brigham Young University
Preston A. Jackson , Brigham Young University
pp. 228
Session 10: Compilation Techniques

Performance Modeling of Reconfigurable SoC Architectures and Energy-Efficient Mapping of a Class of Applications (Abstract)

Jingzhao Ou , University of Southern California
Seonil Choi , University of Southern California
Viktor K. Prasanna , University of Southern California
pp. 241

Reconfigurable Computing Application Frameworks (Abstract)

Anthony L. Slade , Brigham Young University
Brent E. Nelson , Brigham Young University
Brad L. Hutchings , Brigham Young University
pp. 251
Posters

Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design (PDF)

M. Haldar , AccelChip, Inc.
P. Banerjee , Northwestern University
D. Bagchi , AccelChip, Inc.
V. Kim , AccelChip, Inc.
R. Uribe , AccelChip, Inc.
A. Nayak , AccelChip, Inc.
pp. 263

FPGA-based SIMD Processor (PDF)

Philip H.W. Leong , The Chinese University of Hong Kong
Stanley Y.C. Li , The Chinese University of Hong Kong
Gap C.K. Cheuk , The Chinese University of Hong Kong
K.H. Lee , The Chinese University of Hong Kong
pp. 267

Implementation of Three-Dimensional FPGA-Based FDTD Solvers: An Architectural Overview (PDF)

Dennis W. Prather , University of Delaware
Fernando E. Ortiz , University of Delaware
James P. Durbano , EM Photonics, Inc.
John R. Humphrey , University of Delaware
Mark S. Mirotznik , The Catholic University of America
pp. 269

A Pipelined SoPC Architecture for 2.5 Gbps Network Processing (PDF)

Xing Yu , Queen?s University Belfast
Ciaran Toal , Queen?s University Belfast
Sakir Sezer , Queen?s University Belfast
pp. 271

A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs (Abstract)

K. Benkrid , The Queen?s University of Belfast
A. Benkrid , The Queen?s University of Belfast
D. Crookes , The Queen?s University of Belfast
pp. 273

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms (PDF)

Francky Catthoor , IMEC vzw; Vrije Universiteit Brussel
Javier Resano , Universidad Complutense de Madrid
Diederik Verkest , IMEC vzw; Katholieke Universiteit Leuven
Daniel Mozos , Universidad Complutense de Madrid
Serge Vernalde , IMEC vzw
pp. 278

A Logic Based Hardware Development Environment (PDF)

S. Belkacemi , The Queen?s University of Belfast
K. Benkrid , The Queen?s University of Belfast
D. Crookes , The Queen?s University of Belfast
pp. 280

Fabric-Based Systems: Model, Tools, Applications (PDF)

Kevin McCabe , Los Alamos National Laboratory
Maya Gokhale , Los Alamos National Laboratory
Christophe Wolinski , Los Alamos National Laboratory
pp. 288

Exploiting Reconfigurable Hardware for Network Security (PDF)

Jim Torresen , University of Oslo
Oddvar Soraasen , University of Oslo
Shaomeng Li , University of Oslo
pp. 292

A Second Generation Embedded Reconfigurable Input Device for Kinetically Challenged Persons (PDF)

Stamatios Sotiropoulos , Technical University of Crete
Kyprianos Papademetriou , Technical University of Crete
Apostolos Dollas , Technical University of Crete
pp. 294

Performance and Area Modeling of Complete FPGA Designs in the presence of Loop Transformations (PDF)

K.R. Shesha Shayee , University of Southern California
Pedro C. Diniz , USC Information Sciences Institute
Joonseok Park , USC Information Sciences Institute
pp. 296

Synthesis and Estimation of Memory Interfaces for FPGA-based Reconfigurable Computing Engines (Abstract)

Pedro C. Diniz , University of Southern California
Joonseok Park , University of Southern California
pp. 297

Linear Placement for Static / Dynamic Reconfiguration in JBits (PDF)

Sharareh Noorbaloochi , University of Minnesota, Minneapolis
Vamsi Krishna Marreddy , University of Minnesota, Minneapolis
Kia Bazargan , University of Minnesota, Minneapolis
pp. 300

Real-time Extensions to a C-like Hardware Description Language (Abstract)

Tim Todman , Imperial College
Wayne Luk , Imperial College
pp. 302

Author Index (PDF)

pp. 311
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