The Community for Technology Leaders
Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2002)
Napa, California
Sept. 22, 2002 to Sept. 24, 2002
ISSN: 1082-3409
ISBN: 0-7695-1801-X
TABLE OF CONTENTS
Introduction
Session 1: Applications I

A Massively Parallel RC4 Key Search Engine (Abstract)

K. H. Tsoi , Chinese University of Hong Kong
P. H. W. Leong , Chinese University of Hong Kong
K. H. Lee , Chinese University of Hong Kong
pp. 13

An FPGA Implementation of Triangle Mesh Decompression (Abstract)

Tulika Mitra , National University of Singapore
Tzi-cker Chiueh , State University of New York at Stony Brook
pp. 22
Session 2: Networking I

Control and Configuration Software for a Reconfigurable Networking Hardware Platform (Abstract)

Todd S. Sproull , Washington University at Saint Louis
John W. Lockwood , Washington University at Saint Louis
David E. Taylor , Washington University at Saint Louis
pp. 45
Session 3: Tool I

Peer-to-Peer Hardware-Software Interfaces for Reconfigurable Fabrics (Abstract)

Mihai Budiu , Carnegie Mellon University
Ashwin R. Bharambe , Carnegie Mellon University
Seth Copen Goldstein , Carnegie Mellon University
Mahim Mishra , Carnegie Mellon University
pp. 57

Coarse-Grain Pipelining on Multiple FPGA Architectures (Abstract)

Pedro C. Diniz , University of Southern California
Mary Hall , University of Southern California
Byoungro So , University of Southern California
Heidi Ziegler , University of Southern California
pp. 77
Session 4: Template Matching

FPGA-Based Template Matching Using Distance Transforms (Abstract)

A. Kugel , University of Mannheim
R. Männer , University of Mannheim
S. Hezel , University of Mannheim
D. M. Gavrila , DaimlerChrysler Research
pp. 89

Reconfigurable Shape-Adaptive Template Matching Architectures (Abstract)

Peter Y.K. Cheung , Imperial College
Jörn Gause , Imperial College
Wayne Luk , Imperial College
pp. 98
Session 5: Networking II

Assisting Network Intrusion Detection with Reconfigurable Hardware (Abstract)

D. Carver , Brigham Young University
R. Franklin , Brigham Young University
B. L. Hutchings , Brigham Young University
pp. 111

GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing (Abstract)

Peter Bellows , University of Southern California
Brian Schott , University of Southern California
Tom Lehman , University of Southern California
Keith D. Underwood , University of Southern California
Jaroslav Flidr , University of Southern California
pp. 121

Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic (Abstract)

Gokhan Memik , University of California at Los Angeles
Seda Ogrenci Memik , University of California at Los Angeles
William H. Mangione-Smith , University of California at Los Angeles
pp. 131
Session 6: Architecture I

Using On-Chip Configurable Logic to Reduce Embedded System Software Energy (Abstract)

Brian Grattan , University of California at Riverside
Jason Villarreal , University of California at Riverside
Frank Vahid , University of California at Riverside and University of California at Irvine
Greg Stitt , University of California at Riverside
pp. 143

Queue Machines: Hardware Compilation in Hardware (Abstract)

Benjamin Levine , Carnegie Mellon University
Benjamin Ylvisaker , Carnegie Mellon University
Herman Schmit , Carnegie Mellon University
pp. 152
Session 7: Applications II

Custom Computing Machines for the Set Covering Problem (Abstract)

Christian Plessl , Swiss Federal Institute of Technology
Marco Platzner , Swiss Federal Institute of Technology
pp. 163

Using Floating-Point Arithmetic on FPGAs to Accelerate Scientific N-Body Simulations (Abstract)

Reinhard Männer , University of Mannheim
Andreas Kugel , University of Mannheim
Gerhard Lienhart , University of Mannheim
pp. 182
Session 8: Architecture II

Mobile Memory: Improving Memory Locality in Very Large Reconfigurable Fabrics (Abstract)

Rong Yan , Carnegie Mellon University
Seth C. Goldstein , Carnegie Mellon University
pp. 195

Hardware-Assisted Fast Routing (Abstract)

John Wawrzynek , University of California at Berkeley
Randy Huang , University of California at Berkeley
André DeHon , California Institute of Technology
pp. 205
Session 9: Tools II

Optimum Wordlength Allocation (Abstract)

Wayne Luk , Imperial College
Peter Y. K. Cheung , Imperial College
George A. Constantinides , Imperial College
pp. 219

Pr?cis: A Design-Time Precision Analysis Tool (Abstract)

Mark L. Chang , University of Washington
Scott Hauck , University of Washington
pp. 229

Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems (Abstract)

Fadi J. Kurdahi , University of California at Irvine
Dhananjay Kulkarni , University of California at Riverside
Walid A. Najjar , University of California at Riverside
Robert Rinker , University of Idaho
pp. 239
Session 10: Image Compression

Hyperspectral Image Compression on Reconfigurable Platforms (Abstract)

Scott Hauck , University of Washington
Thomas W. Fry , University of Washington
pp. 251

MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64 (Abstract)

Stamatis Vassiliadis , Delft University of Technology
Jos T. J. van Eijndhoven , Philips Research
Kees Vissers , TriMedia Technologies, Inc.
Mihai Sima , Delft University of Technology and Philips Research
Sorin Cotofana , Delft University of Technology
pp. 261
Poster Session 1

On Sparse Matrix-Vector Multiplication with FPGA-Based System (PDF)

Hossam ElGindy , University of New South Wales
Yen-Liang Shue , University of New South Wales
pp. 273

Implementing a Simple Continuous Speech Recognition System on an FPGA (PDF)

S. J. Melnikoff , University of Birmingham
S. F. Quigley , University of Birmingham
M. J. Russell , University of Birmingham
pp. 275

On Implementing a Configware/Software SAT Solver (PDF)

N. A. Reis , Technical University of Lisbon
J. T. de Sousa , Technical University of Lisbon
pp. 282

Reconfigurable Object Detection in FLIR Image Sequences (PDF)

Peter M. Athanas , Virginia Polytechnic Institute and State University
Jonathan E. Scalera , Virginia Polytechnic Institute and State University
Amitabh Mishra , Virginia Polytechnic Institute and State University
Creed F. Jones III , Virginia Polytechnic Institute and State University
A. Lynn Abbott , Virginia Polytechnic Institute and State University
Maneesh Soni , Virginia Polytechnic Institute and State University
Mark B. Bucciero , Virginia Polytechnic Institute and State University
pp. 284

TCP-Stream Reassembly and State Tracking in Hardware (PDF)

Marc Necker , Georgia Institute of Technology
Didier Contis , Georgia Institute of Technology
David Schimmel , Georgia Institute of Technology
pp. 286
Poster Session 2

Module Generators Driving the Compilation for Adaptive Computing Systems (PDF)

Nico Kasprzyk , Technical University Braunschweig
Andreas Koch , Technical University Braunschweig
pp. 293

System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems (PDF)

Jarkko Niittylahti , Tampere University of Technology
Tero Rissa , Tampere University of Technology
Milan Vasilko , Bournemouth University
pp. 295

Compiling ATR Probing Codes for Execution on FPGA Hardware (PDF)

W. Böhm , Colorado State University and University of California at Riverside
R. Beveridge , Colorado State University and University of California at Riverside
B. Draper , Colorado State University and University of California at Riverside
M. Chawathe , Colorado State University and University of California at Riverside
W. Najjar , Colorado State University and University of California at Riverside
C. Ross , Colorado State University and University of California at Riverside
pp. 301

The Effects of Datapath Placement and C-Slow Retiming on Three Computational Benchmarks (PDF)

John Wawrzynek , University of California at Berkeley
Nicholas Weaver , University of California at Berkeley
pp. 303
Poster Session 3

A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing (PDF)

Yoshito Mekada , Nagoya University
Tsutomu Yoshinaga , The University of Electro-Communications
Masamichi Nagafuchi , Utsunomiya University
Takashi Yokota , Utsunomiya University
Takanobu Baba , Utsunomiya University
Kanemitsu Ootsu , Utsunomiya University
pp. 307

The Design of the Amalgam Reconfigurable Cluster (PDF)

Chi-Wei Wang , University of Illinois at Urbana-Champaign
Joshua D. Walstrom , University of Illinois at Urbana-Champaign
Derek B. Gottlieb , University of Illinois at Urbana-Champaign
Jeffrey J. Cook , University of Illinois at Urbana-Champaign
Steve Ferrera , University of Illinois at Urbana-Champaign
Nicholas P. Carter , University of Illinois at Urbana-Champaign
pp. 309

Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor (PDF)

Derek B. Gottlieb , University of Illinois at Urbana-Champaign
Chi-Wei Wang , University of Illinois at Urbana-Champaign
Nicholas P. Carter , University of Illinois at Urbana-Champaign
Joshua D. Walstrom , University of Illinois at Urbana-Champaign
Jeffrey J. Cook , University of Illinois at Urbana-Champaign
Steven Ferrera , University of Illinois at Urbana-Champaign
pp. 311
Poster Session 4

Customising Floating-Point Designs (Abstract)

Nabeel Shirazi , Xilinx, Inc.
Altaf Abdul Gaffar , Imperial College
Wayne Luk , Imperial College
Peter Y. K. Cheung , Imperial College
pp. 315

Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes (PDF)

Tim Courtney , Queen?s University Belfast
Richard Turner , Queen?s University Belfast
Roger Woods , Queen?s University Belfast
pp. 318
Author Index

Author Index (PDF)

pp. 321
89 ms
(Ver )