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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2001)
Rohnert Park, California
Apr. 29, 2001 to May 2, 2001
ISBN: 0-7695-2667-5
TABLE OF CONTENTS
Session 1: DSP

Parallelization of MATLAB Applications for a Multi-FPGA System (Abstract)

Anshuman Nayak , Northwestern University
Malay Haldar , Northwestern University
Prith Banerjee , Northwestern University
Alok Choudhary , Northwestern University
pp. 1-9

Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems (Abstract)

Bernadeta Srijanto , University of Tennessee
Danny Newport , University of Tennessee
Mike Langston , University of Tennessee
Chandra Tan , University of Tennessee
Nabil Kerkiz , University of Tennessee
Don Bouldin , University of Tennessee
Sze-Wei Ong , University of Tennessee
pp. 10-20

Parameterized Module Generator for an FPGA-Based Electronic Cochlea (Abstract)

P. H. W. Leong , Chinese University of Hong Kong
C. T. Jin , University of Sydney
M. P. Leong , Chinese University of Hong Kong
pp. 21-30
Session 2: Tools

Instrumenting Bitstreams for Debugging FPGA Circuits (Abstract)

Brent Nelson , Brigham Young University
Paul Graham , Brigham Young University
Brad Hutchings , Brigham Young University
pp. 41-50
Session 3: Arithmetic

The Multiple Wordlength Paradigm (Abstract)

Peter Y.K. Cheung , Imperial College
George A. Constantinides , Imperial College
Wayne Luk , Imperial College
pp. 51-60

FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization (Abstract)

Miloš D. Ercegovac , University of California at Los Angeles
Zhijun Huang , University of California at Los Angeles
pp. 61-70
Session 4: JBits
Session 5: Architecture I

Architecture and Application of PLATO, A Reconfigurable Active Network Platform (Abstract)

Konstantinos Harteros , Institute of Computer Science (ICS) - FORTH
Nikolaos Aslanides , Technical University of Crete
Kyprianos Papademetriou , Technical University of Crete
Nikolaos Chrysos , Institute of Computer Science (ICS) - FORTH
Apostolos Dollas , Technical University of Crete
Euripides Sotiriades , Technical University of Crete
Dionisios Pnevmatikatos , Technical University of Crete
Stamatios Kavvadias , Technical University of Crete
Emanouil Antonidakis , Technological and Educational Institute of Crete
Sotirios Zogopoulos , Technical University of Crete
Nikolaos Petrakis , Technological and Educational Institute of Crete
pp. 101-110

Totem: Custom Reconfigurable Array Generation (Abstract)

Scott Hauck , University of Washington
Katherine Compton , Northwestern University
pp. 111-119

A Cellular Automata System with FPGA (Abstract)

Tsutomu Hoshino , University of Tsukuba
Tsutomu Maruyama , University of Tsukuba
Tomoyoshi Kobori , University of Tsukuba
pp. 120-129
Session 6: Fault Tolerance

A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System (Abstract)

Davide Salvi , Istituto di Fisica Cosmica "G. Occhialini", CNR
Monica Alderighi , Istituto di Fisica Cosmica "G. Occhialini", CNR
Fabio Casini , Universita? di Milano
Giacomo R. Sechi , Istituto di Fisica Cosmica "G. Occhialini", CNR
Sergio D'Angelo , Istituto di Fisica Cosmica "G. Occhialini", CNR
pp. 130-136

Column-Based Precompiled Configuration Techniques for FPGA (Abstract)

Wei-Je Huang , Stanford University
Edward J. McCluskey , Stanford University
pp. 137-146
Session 7: Architecture II

Configuration Compression for Virtex FPGAs (Abstract)

Zhiyuan Li , Northwestern University
Scott Hauck , University of Washington
pp. 147-159

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia (Abstract)

Sorin Cotofana , Delft University of Technology
Mihai Sima , Delft University of Technology and Philips Research
Jos T. J. van Eijndhoven , Philips Research
Stamatis Vassiliadis , Delft University of Technology
Kees Vissers , TriMedia Technologies, Inc.
pp. 160-169

Pilchard — A Reconfigurable Computing Platform with Memory Slot Interface (Abstract)

K. H. Lee , Chinese University of Hong Kong
C. M. Kwok , Chinese University of Hong Kong
O. Y. H. Cheung , Chinese University of Hong Kong
P. H. W. Leong , Chinese University of Hong Kong
M. P. Leong , Chinese University of Hong Kong
M. Y. Wong , Chinese University of Hong Kong
T. Tung , Chinese University of Hong Kong
pp. 170-179
Session 8: Applications I

Acceleration of a 2D-FFT on an Adaptable Computing Cluster (Abstract)

Keith D. Underwood , Clemson University
Walter B. Ligon, III , Clemson University
Ron R. Sass , Clemson University
pp. 180-189

Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA (Abstract)

D. Crookes , The Queen?s University of Belfast
K. Benkrid , The Queen?s University of Belfast
A. Benkrid , The Queen?s University of Belfast
pp. 190-198
Session 9: Image Processing

An Application-Specific Compiler for High-Speed Binary Image Morphology (Abstract)

Scott Hemmert , Brigham Young University
Brad Hutchings , Brigham Young University
Anshul Malvi , Brigham Young University
pp. 199-208

One-Step Compilation of Image Processing Applications to FPGAs (Abstract)

M. Chawathe , Colorado State University
R. Rinker , Colorado State University
J. Hammes , Colorado State University
C. Ross , Colorado State University
W. Najjar , Colorado State University
B. Draper , Colorado State University
A. P. W. Böhm , Colorado State University
pp. 209-218

High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons (Abstract)

D. Crookes , The Queen?s University of Belfast
J. Smith , VisiCom division of Titan Corp.
A. Benkrid , The Queen?s University of Belfast
K. Benkrid , The Queen?s University of Belfast
pp. 219-226
Session 10: Applications II

Fast Regular Expression Matching Using FPGAs (Abstract)

Reetinder Sidhu , University of Southern California
Viktor K. Prasanna , University of Southern California
pp. 227-238

A Configurable Hardware/Software Approach to SAT Solving (Abstract)

M. Abramovici , Agere Systems
J. T. de Sousa , Technical University of Lisbon
J. M. da Silva , Technical University of Lisbon
pp. 239-248
Posters

The Development of an Operating System for Reconfigurable Computing (PDF)

David Kearney , University of South Australia
Grant Wigley , University of South Australia
pp. 249-250

JBits™ Design Abstractions (PDF)

Steven A. Guccione , Xilinx, Inc.
Cameron Patterson , Xilinx, Inc.
pp. 251-252

A Behavioral Synthesis Estimation Interface for Configurable Computing (PDF)

Ashok Venkatachar , University of Southern California
Pedro Diniz , University of Southern California
pp. 253-254

System on a FPGA Virtual Concatenation (PDF)

Claire Greenwood , Nortel Networks
Marc Carson , Nortel Networks
Eimear Stewart , The Queen?s University of Belfast
Sakir Sezer , The Queen?s University of Belfast
pp. 257-258

Circlets: Circuitry over the Internet (PDF)

Irwin Kennedy , University of Edinburgh
Gordon Brebner , University of Edinburgh
pp. 261-262

Evaluation of Reconfigurable Cache Module Architecture (Abstract)

Abhishek Singhal , Iowa State University
Arun Somani , Iowa State University
Akhilesh Tyagi , Iowa State University
pp. 263-266

An External Memory Interface for FPGA-Based Computing Engines (PDF)

Joonseok Park , University of Southern California
Pedro Diniz , University of Southern California
pp. 267-268

A SW/HW Interface API for Java/FPGA Co-Designed Applets (PDF)

Rudy Lauwereins , K. U. Leuven
Hugo De Man , IMEC and K. U. Leuven
Yajun Ha , IMEC and K. U. Leuven
pp. 269-270

The FPGA Development System CHDL (PDF)

R. Männer , Universität Mannheim
A. Kugel , Universität Mannheim
K. Kornmesser , Universität Mannheim
pp. 271-272

Mutable Functional Units: Initial Results (PDF)

Yong Luo , Intel Corporation
Yan Solihin , University of Illinois at Urbana-Champaign
Dominique Lavenier , IRISA/CNRS
Kirk W. Cameron , Florida Institute of Technology
Maya Gokhale , Los Alamos National Laboratory
pp. 283-284

Rapid Synthesis of Pattern Classification Circuits (PDF)

Kenneth Mackenzie , Georgia Institute of Technology
Adam Johnson , Georgia Institute of Technology
pp. 285-286

The Effect of FPGA Granularity on Video Codec Implementations (PDF)

J? Gause , Imperial College
Holger Kropp , University of Hannover
Wayne Luk , Imperial College
Carsten Reuter , University of Hannover
Peter Y. K. Cheung , Imperial College
pp. 287-288

Accelerating Statistical Texture Analysis with an FPGA-DSP Hybrid Architecture (PDF)

F. Ibarra Pic? , Universidad de Alicante
V. C?rcoles , Universidad de Alicante
S. Cuenca Asensi , Universidad de Alicante
pp. 289-290

Hardware Implementation of Automated Sensor Self-Validation System for Cupola Furnaces (Abstract)

Mohamed Abdelrahman , Tennessee Technological University
Roger L. Haggard , Tennessee Technological University
Wagdy H. Mahmoud , Tennessee Technological University
pp. 291-299

Reconfigurable Designs for Ray Tracing (PDF)

Wayne Luk , Imperial College
Tim Todman , Imperial College
pp. 300-301

Manufacturing Shop-Floor Supercomputer for Distributed Simulation and Control (PDF)

J. Patel , Penn State University
V. Prabhu , Penn State University
pp. 302-303

Pipelined Function Evaluation on FPGAs (Abstract)

Wayne Luk , Imperial College
Henry Styles , Imperial College
Nicolas Boullis , Ecole Normale Superieure de Lyon
Oskar Mencer , Lucent, Bell Labs
pp. 304-306
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