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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (2000)
Napa, California
Apr. 17, 2000 to Apr. 19, 2000
ISSN: 1082-3409
ISBN: 0-7695-0871-5
TABLE OF CONTENTS
Session 1: Architecture, Chair: André DeHon

Design of a VLIW Compute Accelerator on the Transmogrifier-2 (Abstract)

L. Louis Zhang , University of Toronto
David M. Lewis , University of Toronto
Qiang Wang , University of Toronto
pp. 3

A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Problems (Abstract)

Tracy Larrabee , University of California at Santa Cruz
Mark J. Boyd , University of California at Santa Cruz
pp. 13

Configuration Caching Management Techniques for Reconfigurable Computing (Abstract)

Katherine Compton , Northwestern University
Scott Hauck , University of Washington
Zhiyuan Li , Northwestern University
pp. 22
Session 2: Compilation 1, Chair: Wayne Luk

A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems (Abstract)

A. Jones , Northwestern University
S. Periyacheri , Northwestern University
P. Banerjee , Northwestern University
M. Walkden , Northwestern University
S. Hauck , Northwestern University
P. Joisha , Northwestern University
A. Nayak , Northwestern University
M. Haldar , Northwestern University
A. Kanhare , Northwestern University
A. Choudhary , Northwestern University
D. Zaretsky , Northwestern University
N. Shenoy , Northwestern University
C. Bachmann , Northwestern University
pp. 39

Stream-Oriented FPGA Computing in the Streams-C High Level Language (Abstract)

Jeff Arnold , Adaptive Silicon, Inc.
Maya B. Gokhale , Los Alamos National Laboratory
Janice M. Stone , Los Alamos National Laboratory
Mirek Kalinowski , Sarnoff Corporation
pp. 49
Session 3: Applications 1, Chair: Philip Freiden

A Reconfigurable Computing Architecture for Microsensors (Abstract)

Mark Falco , Sanders, a Lockheed Martin Company
Stephen Scalera , Sanders, a Lockheed Martin Company
Brent Nelson , Brigham Young University
pp. 59

FPGA Implementation of a Microcoded Elliptic Curve Cryptographic Processor (Abstract)

W.K. Wong , Chinese University of Hong Kong
P.H.W. Leong , Chinese University of Hong Kong
K.W. Ma , Chinese University of Hong Kong
K.H. Leung , Chinese University of Hong Kong
pp. 68
Session 4: Compilation 2, Chair: Scott Hauck

Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines (Abstract)

Pedro Diniz , University of Southern California
Joonseok Park , University of Southern California
pp. 91

A C to HDL Compiler for Pipeline Processing on FPGAs (Abstract)

Tsutomu Hoshino , University of Tsukuba
Tsutomu Maruyama , University of Tsukuba
pp. 101
Session 5: Cryptographic Applications, Chair: John McHenry

A Bit-Serial Implementation of the International Data Encryption Algorithm IDEA (Abstract)

K.H. Tsoi , Chinese University of Hong Kong
O.Y.H. Cheung , Chinese University of Hong Kong
P.H.W. Leong , Chinese University of Hong Kong
M.P. Leong , Chinese University of Hong Kong
pp. 122

An Adaptive Cryptographic Engine for IPSec Architectures (Abstract)

Jose D. P. Rolim , University of Southern California
Andreas Dandalis , University of Southern California
Viktor K. Prasanna , University of Southern California
pp. 132
Session 6: Programming Tools, Chair: Brad Hutchings

Death of the RLOC? (Abstract)

Satnam Singh , Xilinx Inc.
pp. 145
Session 7: Fault Tolerance, Chair: Philip Kuekes

Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration (Abstract)

Charles Stroud , University of Kentucky
Miron Abramovici , Bell Labs - Lucent Technologies
Brandon Skaggs , University of Kentucky
John Emmert , University of Kentucky
pp. 165

An ACS Robotic Control Algorithm with Fault Tolerant Capabilities (Abstract)

Edward J. McCluskey , Stanford University
Nirmal Saxena , Stanford University
Shu-Yi Yu , Stanford University
pp. 175

Tunable Fault Tolerance for Runtime Reconfigurable Architectures (Abstract)

Peter M. Kamarchik , Carnegie Mellon University
Steven K. Sinha , Carnegie Mellon University
Seth C. Goldstein , Carnegie Mellon University
pp. 185
Session 8: Wireless Applications, Chair: Tom Kean

Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs (Abstract)

Michael Rice , Brigham Young University
Chris Dick , Xilinx Inc.
Fred Harris , California State University at San Diego
pp. 195

Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems (Abstract)

Jürgen Becker , Darmstadt University of Technology
Ahmad Alsolaim , Ohio University
Janusz Starzyk , Ohio University
Manfred Glesner , Darmstadt University of Technology
pp. 205
Session 9: Applications 2, Chair: Mike Butts

Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation Engine (PDF)

Peter Athanas , Virginia Tech
Euripides Sotiriades , Technical University of Crete
Apostolos Dollas , Technical University of Crete
pp. 227

An FPGA-Based Coprocessor for the Parsing of Context-Free Grammars (Abstract)

Cristian Ciressan , Ecole Polytechnique F?d?rale de Lausanne
Eduardo Sanchez , Ecole Polytechnique F?d?rale de Lausanne
Jean-Cedric Chappelier , Ecole Polytechnique F?d?rale de Lausanne
Martin Rajman , Ecole Polytechnique F?d?rale de Lausanne
pp. 236
Session 10: Applications 3, Chair: Don Bouldin

A Reliable LZ Data Compressor on Reconfigurable Coprocessors (Abstract)

Edward J. McCluskey , Stanford University
Nirmal Saxena , Stanford University
Wei-Je Huang , Stanford University
pp. 249

EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroiding (Abstract)

Sergio D'Angelo , Istituto di Fisica Cosmica ?G. Occhialini?
Monica Alderighi , Istituto di Fisica Cosmica ?G. Occhialini?
Giacomo R. Sechi , Istituto di Fisica Cosmica ?G. Occhialini?
pp. 259

Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware (Abstract)

Brian Bray , Sandia National Laboratories
Steve Morrison , Brigham Young University
Michael J. Wirthlin , Brigham Young University
Paul Graham , Brigham Young University
pp. 267
Poster Session 1

Configuration Relocation and Defragmentation for Reconfigurable Computing (Abstract)

Katherine Compton , Northwestern University
Scott Hauck , University of Washington
Stephen Knol , Northwestern University
James Cooley , Northwestern University
pp. 279

Hardware Accelerator for Subgraph Isomorphism Problems (Abstract)

Kouji Konishi , Toyohashi University of Technology
Lerdtanaseangtham Udorn , Toyohashi University of Technology
Shuichi Ichikawa , Toyohashi University of Technology
pp. 283

Reconfigurable Array Media Processor (RAMP) (Abstract)

Kamlesh Rath , University of Texas at Dallas
Sirisha Tangirala , University of Texas at Dallas
Poras Balsara , University of Texas at Dallas
Patrick Friel , University of Texas at Dallas
John Wadley , Texas Instruments
Jose Flores , Texas Instruments
pp. 287

Internet Connected FPGAs (Abstract)

Michael John Sebastian Smith , University of Hawaii
Hamish Fallside , Xilinx Inc
pp. 289

A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems (Abstract)

Hideharu Amano , Keio University
Yuichiro Shibata , Keio University
Hitoshi Kurosawa , Keio University
O. Yamamoto , Keio University
pp. 291
Poster Session 2

A Virtual Hardware System on a Dynamically Reconfigurable Logic Device (Abstract)

H. Amano , Keio University
Y. Shibata , Keio University
M. Uno , Keio University
K. Furuta , NEC Corp.
T. Fujii , NEC Corp.
M. Motomura , NEC Corp.
pp. 295

Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures (Abstract)

R. Hermida , Universidad Complutense
N. Bagherzadeh , University of California at Irvine
R. Maestre , Universidad Complutense
M. Fernandez , Universidad Complutense
F.J. Kurdahi , University of California at Irvine
H. Singh , University of California at Irvine
pp. 297

A Communication Scheduling Algorithm for Multi-FPGA Systems (Abstract)

Jinwoo Suh , University of Southern California
Dong-In Kang , University of Southern California
Stephen P. Crago , University of Southern California
pp. 299

Preemptive Multitasking on FPGAs (Abstract)

R. Männer , University of Mannheim
L. Levinson , Weizmann Institute of Science
H. Simmler , University of Mannheim
M. Sessler , University of Mannheim
pp. 301

BigSky-An On-Line Arithmetic Design Tool for FPGAs (Abstract)

Robert McIlhenny , University of California at Los Angeles
M.D. Ercegovac , University of California at Los Angeles
Aaron Schneider , University of California at Los Angeles
pp. 303

Multiple Precision for Resource Minimization (Abstract)

Wayne Luk , Imperial College
George A. Constantinides , Imperial College
Peter Y.K. Cheung , Imperial College
pp. 307
Poster Session 3

An FPGA-Based Array Processor for an Ionospheric-Imaging Radar (Abstract)

Chucai Zhou , University of Washington
Tim Tuan , University of Washington
John Sahr , University of Washington
Frank Lind , University of Washington
Miguel Figueroa , University of Washington
Chris Diorio , University of Washington
pp. 313
Poster Session 4

FCCMS and the Memory Wall (Abstract)

S. Derrien , IRISA
pp. 329

A C to Hardware/Software Compiler (Abstract)

Seda Ogrenci , Northwestern University
Majid Sarrafzadeh , Northwestern University
Ryan Kastner , Northwestern University
Kiarash Bazargan , Northwestern University
pp. 331

Evaluating Hardware Compilation Techniques (Abstract)

Wayne Luk , Imperial College
Markus Weinhardt , Imperial College
pp. 333

A Networked FPGA-Based Hardware Implementation of a Neural Network Application (Abstract)

Andres Perez-Uribe , Swiss Federal Institute of Technology
Ralph Hoffmann , Swiss Federal Institute of Technology
Eduardo Sanchez , Swiss Federal Institute of Technology
Christof Teuscher , Swiss Federal Institute of Technology
Héctor Fabio Restrepo , Swiss Federal Institute of Technology
pp. 337

Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing Systems (Abstract)

Katsuharu Suzuki , University of California at Santa Cruz
Zhao Fang , University of California at Santa Cruz
Wayne W.-M. Dai , University of California at Santa Cruz
Michael X. Wang , University of California at Santa Cruz
pp. 339

An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing (Abstract)

Richard Turner , Queen's University of Belfast
Timothy Courtney , Queen's University of Belfast
Roger Woods , Queen's University of Belfast
pp. 341

Author Index (PDF)

pp. 347
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