Program Committee (PDF)

A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications (Abstract)

Exploring Optimal Cost-Performance Designs for Raw Microprocessors (Abstract)

The NAPA Adaptive Processing Architecture (Abstract)

A Stream-Based Configurable Computing Radio Testbed (Abstract)

Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation (Abstract)

New FPGA Architecture for Bit-Serial Pipeline Datapath (Abstract)

Plastic Cell Architecture: Towards Reconfigurable Computing for General-Purpose (Abstract)

The Design and Implementation of a Context Switching FPGA (Abstract)

A Run-Time Reconfigurable Engine for Image Interpolation (Abstract)

Hardware/Software Integration in Solar Polarimetry (Abstract)

An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA Systems (Abstract)

Specifying and Compiling Applications for RaPiD (Abstract)

NAPA C: Compiling for a Hybrid RISC/FPGA Architecture (Abstract)

Configuration Compression for the Xilinx XC6200 FPGA (Abstract)

Automating Production of Run-Time Reconfigurable Designs (Abstract)

Object Oriented Circuit-Generators in Java (Abstract)

PAM-Blox: High Performance FPGA Design for Adaptive Computing (Abstract)

JHDL - An HDL for Reconfigurable Systems (Abstract)

Accelerating Boolean Satisfiability with Configurable Hardware (Abstract)

Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean Satisfiability (Abstract)

A Re-evaluation of the Practicality of Floating-Point Operations on FPGAs (Abstract)

A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor Architectures (Abstract)

A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure (Abstract)

Accelerating Adobe Photoshop with the Reconfigurable Logic (Abstract)

Analysis of the XC6000 Architecture for Embedded System Design (Abstract)

A FPGA Based Forth Microprocessor (Abstract)

PROGRAPE-1: A Programmable Special-Purpose Computer for Many-Body Simulations (Abstract)

RVC - A Reconfigurable Coprocessor for Vector Processing Applications (Abstract)

The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design Methodology. (Abstract)

50 kHz Pattern Recognition on the Large FPGA Processor Enable++ (Abstract)

An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration (Abstract)

Mapping the MD5 Hash Algorithm onto the NAPA Architecture (Abstract)

General Purpose vs. Custom FCCM's: a Comparison of Splash2, Quickturn RPM, and GE1 for Golomb Ruler Derivation (Abstract)

An Architecture Simulator for National Semiconductor's Adaptive Processing Architecture (NAPA) (Abstract)

Benchmarking Technology for Configurable Computing System (Abstract)

Reconfigurable Processor Architectures Exploiting High Bandwidth Optical Channels (Abstract)

Some Applications of FPGAs in Bio-Inspired Hardware (Abstract)

A Prototype System for Rapid Application Development using Dynamically Reconfigurable Hardware (Abstract)

Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application (Abstract)

An FPGA Implementation of GENET for Solving Graph Coloring Problems (Abstract)

SLAAC: A Distributed Architecture for Adaptive Computing (Abstract)

RENCO: A Reconfigurable Network Computer (Abstract)

Hardware Implementation of Generalized Profile Search on the GENSTORM Machine (Abstract)

FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for Smartcards (Abstract)

Characterization and Parameterization of a Pipeline Reconfigurable FPGA (Abstract)

A FPGA-Based Custom Computing System for Solving the Assignment Problem (Abstract)

Circlets: Circuits as Applets (Abstract)

Dynamic Reconfiguration to Support Concurrent Applications (Abstract)

A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing (Abstract)

Frequency-Domain Sonar Processing in FPGAs and DSPs (Abstract)

Dynamic Specialization of XC6200 FPGAs by Partial Evaluation (Abstract)

DES Key Breaking, Encryption and Decryption on the XC6216 (Abstract)

An Effective Design System for Dynamically Reconfigurable Architectures (Abstract)

Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained Architectures (Abstract)

Fast Partial Reconfiguration for FCCMs (Abstract)

Reconfigurable Hardware as Shared Resource for Parallel Threads (Abstract)

Digit-Serial DSP Library for Optimized FPGA Configuration (Abstract)

A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable Systems (Abstract)

High Level Synthesis for Designing Custom Computing Hardware (Abstract)

Temporal Partitioning and Scheduling for Reconfigurable Computing (Abstract)

Implementation of RNS Addition and RNS Multiplication into FPGAs (Abstract)

A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine (Abstract)

Reconfigurable Computing for Space-Time Adaptive Processing (Abstract)

Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks (Abstract)

Implementing C Algorithms in Reconfigurable Hardware Using C2Verilog (Abstract)

Author Index (PDF)