Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (1998)

Napa Valley, California

Apr. 15, 1998 to Apr. 17, 1998

ISSN: 1082-3409

ISBN: 0-8186-8900-5

pp: 335

Jack M. West , Texas Tech University

Nikhil D. Gupta , Texas Tech University

John K. Antonio , Texas Tech University

ABSTRACT

The output of space-time adaptive processing (STAP) is a weighted sum of multiple radar returns, where the weights for each return in the sum are calculated adaptively and in real-time. The most computationally intensive portion of most STAP approaches is the calculation of the adaptive weight values. Calculation of the weights involves solving a set of linear equations based on an estimate of the covariance matrix associated with the radar return data. Existing approaches typically rely on the use of multiple digital signal processors (DSPs) or general-purpose processors (GPPs) to calculate the adaptive weights. These approaches are often based on solving multiple sets of linear equations and require the calculation of numerous vector inner products. This paper proposes the use of FPGAs as vector co-processors capable of performing inner product calculation. Two different "inner-product co-processor" designs are introduced for use with the host DSP or GPP. The first has a multiply-and accumulate structure, and the second uses a reduction-style tree structure having two multipliers and an adder.

INDEX TERMS

CITATION

Jack M. West,
Nikhil D. Gupta,
John K. Antonio,
"Reconfigurable Computing for Space-Time Adaptive Processing",

*Field-Programmable Custom Computing Machines, Annual IEEE Symposium on*, vol. 00, no. , pp. 335, 1998, doi:10.1109/FPGA.1998.707942