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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (1997)
Napa Valley, CA
Apr. 16, 1997 to Apr. 18, 1997
ISSN: 1082-3409
ISBN: 0-8186-8159-4
TABLE OF CONTENTS

Introduction (PDF)

pp. ix
Session 1: Device Architecture

An FPGA architecture for DRAM-based systolic computations (Abstract)

N. Margolus , Center for Comput. Sci., Boston Univ., MA, USA
pp. 2

Garp: a MIPS processor with a reconfigurable coprocessor (Abstract)

J.R. Hauser , California Univ., Berkeley, CA, USA
J. Wawrzynek , California Univ., Berkeley, CA, USA
pp. 12

A time-multiplexed FPGA (Abstract)

J. Wong , Xilinx Inc., San Jose, CA, USA
A. Johnson , Xilinx Inc., San Jose, CA, USA
D. Carberry , Xilinx Inc., San Jose, CA, USA
S. Trimberger , Xilinx Inc., San Jose, CA, USA
pp. 22
Session 2: Communication Applications

An FPGA-based coprocessor for ATM firewalls (Abstract)

P.W. Dowd , Dept. of Defense, Fort Meade, ID, USA
F.A. Pellegrino , Dept. of Defense, Fort Meade, ID, USA
W.B. Cocks , Dept. of Defense, Fort Meade, ID, USA
J.T. McHenry , Dept. of Defense, Fort Meade, ID, USA
T.M. Carrozzi , Dept. of Defense, Fort Meade, ID, USA
pp. 30

A wireless LAN demodulator in a Pamette: design and experience (Abstract)

N. Weste , Dept. of Electron., Macquarie Univ., North Ryde, NSW, Australia
T. McDermott , Dept. of Electron., Macquarie Univ., North Ryde, NSW, Australia
D. Skellern , Dept. of Electron., Macquarie Univ., North Ryde, NSW, Australia
M. Shand , Dept. of Electron., Macquarie Univ., North Ryde, NSW, Australia
T. Percival , Dept. of Electron., Macquarie Univ., North Ryde, NSW, Australia
P. Ryan , Dept. of Electron., Macquarie Univ., North Ryde, NSW, Australia
pp. 40
Session 3: Run Time Reconfiguration

Incremental reconfiguration for pipelined applications (Abstract)

H. Schmit , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 47

Compilation tools for run-time reconfigurable designs (Abstract)

N. Shirazi , Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK
P.Y.K. Cheung , Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK
W. Luk , Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 56

A dynamic reconfiguration run-time system (Abstract)

J. Hogg , Dept. of Comput. Sci., Glasgow Univ., UK
S. Singh , Dept. of Comput. Sci., Glasgow Univ., UK
J. Burns , Dept. of Comput. Sci., Glasgow Univ., UK
A. Donlin , Dept. of Comput. Sci., Glasgow Univ., UK
M. De Wit , Dept. of Comput. Sci., Glasgow Univ., UK
pp. 66
Session 4: Architectures for Run Time Reconfiguration

The swappable logic unit: a paradigm for virtual hardware (Abstract)

G. Brebner , Dept. of Comput. Sci., Edinburgh Univ., UK
pp. 77

The Chimaera reconfigurable functional unit (Abstract)

M.M. Hosler , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
T.W. Fry , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
J.P. Kao , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
S. Hauck , Dept. of Electr. Eng. & Comput. Sci., Northwestern Univ., Evanston, IL, USA
pp. 87
Session 5: Architecture

Computing kernels implemented with a wormhole RTR CCM (Abstract)

R.A. Bittner, Jr. , Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
P.M. Athanas , Dept. of Electr. & Comput. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 98

Mapping applications to the RaPiD configurable architecture (Abstract)

S.G. Berg , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
D.C. Cronquist , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
J. Secosky , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
P. Franklin , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
C. Ebeling , Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA
pp. 106

Defect tolerance on the Teramac custom computer (Abstract)

P. Kuekes , Hewlett-Packard Co., Palo Alto, CA, USA
R. Amerson , Hewlett-Packard Co., Palo Alto, CA, USA
W.B. Culbertson , Hewlett-Packard Co., Palo Alto, CA, USA
R.J. Carter , Hewlett-Packard Co., Palo Alto, CA, USA
G. Snider , Hewlett-Packard Co., Palo Alto, CA, USA
pp. 116
Session 6: Performance

Systems performance measurement on PCI Pamette (Abstract)

M. Shand , Pole Univ. Leonard da Vinci La Defense, France
L. Moll , Pole Univ. Leonard da Vinci La Defense, France
pp. 125

The RAW benchmark suite: computation structures for general purpose computing (Abstract)

V. Lee , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
E. Waingold , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
M. Taylor , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
R. Barua , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
J. Kim , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
J. Babb , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
M. Frank , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
A. Agarwal , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
S. Devabhaktuni , Lab. for Comput. Sci., MIT, Cambridge, MA, USA
pp. 134
Session 7: Software Tools

Automated field-programmable compute accelerator design using partial evaluation (Abstract)

D.M. Lewis , Dept. of Electr. & Comput., Toronto Univ., Ont., Canada
Qiang Wang , Dept. of Electr. & Comput., Toronto Univ., Ont., Canada
pp. 145

FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again) (Abstract)

D. Trainor , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
R. Woods , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
S. Gehring , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
S. Ludwig , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
J. Heron , Inst. of Adv. Microelectron., Queen's Univ., Belfast, UK
pp. 155

High level compilation for fine grained FPGAs (Abstract)

M. Gokhale , David Sarnoff Res. Center, Princeton, NJ, USA
D. Gomersall , David Sarnoff Res. Center, Princeton, NJ, USA
pp. 165
Session 8: CAD Applications

Acceleration of an FPGA router (Abstract)

P.K. Chan , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
M.D.F. Schlag , Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
pp. 175

Fault simulation on reconfigurable hardware (Abstract)

P. Menon , Lucent Technols., Bell Labs., Murray Hill, NJ, USA
M. Abramovici , Lucent Technols., Bell Labs., Murray Hill, NJ, USA
pp. 182
Session 9: Image Processing Applications

Automated target recognition on SPLASH 2 (Abstract)

B.L. Hutchings , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
M. Rencher , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 192

Real-time stereo vision on the PARTS reconfigurable computer (Abstract)

J. Woodfill , Interval Res. Corp., Palo Alto, CA, USA
B. Von Herzen , Interval Res. Corp., Palo Alto, CA, USA
pp. 201

Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing (Abstract)

M. Baxter , Ricoh California Res. Center, Menlo Park, CA, USA
J. Greenbaum , Ricoh California Res. Center, Menlo Park, CA, USA
pp. 211
Session 10: Arithmetic Applications

Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware (Abstract)

C. Paar , Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA
M. Rosner , Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA
pp. 219

Implementation of single precision floating point square root on FPGAs (Abstract)

Wanming Chu , Comput. Archit. Lab., Univ. of Aizu, Aizu-Wakamatsu, Japan
Yamin Li , Comput. Archit. Lab., Univ. of Aizu, Aizu-Wakamatsu, Japan
pp. 226
Poster Papers

Datapath-oriented FPGA mapping and placement for configurable computing (PDF)

J. Wawrzynek , California Univ., Berkeley, CA, USA
T.J. Callahan , California Univ., Berkeley, CA, USA
pp. 234

A parallel hardware evolvable computer POLYP (PDF)

L. Schulte , Inst. fur Molekulare Biotech., Jena, Germany
U. Tangen , Inst. fur Molekulare Biotech., Jena, Germany
J.S. McCaskill , Inst. fur Molekulare Biotech., Jena, Germany
pp. 238

Laser defect correction applications to FPGA based custom computers (PDF)

B. Dufort , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
G.H. Chapman , Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 240

Speech recognition HMM training on reconfigurable parallel processor (PDF)

Hyun-Kyu Yun , Div. of Eng., Brown Univ., Providence, RI, USA
H. Silverman , Div. of Eng., Brown Univ., Providence, RI, USA
A. Smith , Div. of Eng., Brown Univ., Providence, RI, USA
pp. 242

Efficient implementation of the DCT on custom computers (PDF)

B.K. Gunther , Space Centre for Satellite Navigation, Queensland Univ. of Technol., Brisbane, Qld., Australia
Y.Y. Chung , Space Centre for Satellite Navigation, Queensland Univ. of Technol., Brisbane, Qld., Australia
N.W. Bergmann , Space Centre for Satellite Navigation, Queensland Univ. of Technol., Brisbane, Qld., Australia
pp. 244

On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor (PDF)

J. Cong , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J. Peck , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 246

Index of Authors (PDF)

pp. 249
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