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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on (1995)
Napa Valley, California
Apr. 19, 1995 to Apr. 21, 1995
ISBN: 0-8186-7086-X
TABLE OF CONTENTS

Committees (PDF)

pp. viii
Session 1: Custom Computing Platforms

A FCCM for dataflow (spreadsheet) programs (Abstract)

A. Lew , Dept. of Inf. & Comput. Sci., Hawaii Univ., Honolulu, HI, USA
R. Halverson, Jr. , Dept. of Inf. & Comput. Sci., Hawaii Univ., Honolulu, HI, USA
pp. 0002

MORRPH: a modular and reprogrammable real-time processing hardware (Abstract)

T.H. Drayer , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
J.G. Tront , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
W.E. King, IV , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
R.W. Conners , Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 0011

Architecture of a FPGA-based coprocessor: the PAR-1 (Abstract)

J.M. Carrera , ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
E.J. Martinez , ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
S.A. Fernandez , ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
J.M.M. Chaus , ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
pp. 0020
Session 2: Custom Computing Platforms

Teramac-configurable custom computing (Abstract)

R. Amerson , Hewlett-Packard Co., Palo Alto, CA, USA
R.J. Carter , Hewlett-Packard Co., Palo Alto, CA, USA
W.B. Culbertson , Hewlett-Packard Co., Palo Alto, CA, USA
P. Kuekes , Hewlett-Packard Co., Palo Alto, CA, USA
G. Snider , Hewlett-Packard Co., Palo Alto, CA, USA
pp. 0032

Common processor element packaging for CHAMP (Abstract)

B. Box , Lockheed Sanders Avionics, Nashua, NH, USA
J. Nieznanski , Lockheed Sanders Avionics, Nashua, NH, USA
pp. 0039
Session 3: Signal Transport

Design and implementation of a multicomputer interconnection network using FPGAs (Abstract)

Chun-Chao Yeh , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chun-Hsing Wu , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Jie-Yong Juang , Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 0056

Routability improvement using dynamic interconnect architecture (Abstract)

J. Li , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
C.-K. Cheng , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 0061

Reconfigurable real-time signal transport system using custom FPGAs (Abstract)

K. Hayashi , NTT Opt. Network Syst. Labs., Yokosuka, Japan
T. Miyazaki , NTT Opt. Network Syst. Labs., Yokosuka, Japan
K. Shirakawa , NTT Opt. Network Syst. Labs., Yokosuka, Japan
K. Yamada , NTT Opt. Network Syst. Labs., Yokosuka, Japan
N. Ohta , NTT Opt. Network Syst. Labs., Yokosuka, Japan
pp. 0068
Session 4: Run-Time Reconfiguration

Design methodologies for partially reconfigured systems (Abstract)

J.D. Hadley , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
B.L. Hutchings , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 0078

Issues in wireless video coding using run-time-reconfigurable FPGAs (Abstract)

B. Schoner , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
C. Jones , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
J. Villasenor , Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
pp. 0085

Run time reconfiguration of FPGA for scanning genomic databases (Abstract)

E. Lemoine , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
D. Merceron , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 0090

A dynamic instruction set computer (Abstract)

M.J. Wirthlin , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
B.L. Hutchings , Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
pp. 0099
Session 5: Applications I

Emulating static faults using a Xilinx based emulator (Abstract)

R.W. Wieler , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
Z. Zhang , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
R.D. McLeod , Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
pp. 0110

Acceleration of template-based ray casting for volume visualization using FPGAs (Abstract)

M. Dao , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
T.A. Cook , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
D. Silver , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
P.S. D'Urbano , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 0116

Flexible image acquisition using reconfigurable hardware (Abstract)

M. Shand , Res. Lab., Digital Equipment Corp., Paris, France
pp. 0125
Session 6: Compiler Issues I

The Transmogrifier C hardware description language and compiler for FPGAs (Abstract)

D. Galloway , Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
pp. 0136

Architectural descriptions for FPGA circuits (Abstract)

S. Singh , Dept. of Comput. Sci., Glasgow Univ., UK
pp. 0145

Quantitative analysis of floating point arithmetic on FPGA based custom computing machines (Abstract)

N. Shirazi , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
A. Walters , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
P. Athanas , Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
pp. 0155
Session 7: Compiler Issues II

A declarative approach to incremental custom computing (Abstract)

W. Luk , Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 0164

A C++ compiler for FPGA custom execution units synthesis (Abstract)

C. Iseli , Lab. de Syst. Logiques, Ecole Polytech. Federale de Lausanne, Switzerland
E. Sanchez , Lab. de Syst. Logiques, Ecole Polytech. Federale de Lausanne, Switzerland
pp. 0173

Implementing a genetic algorithm on a parallel custom computing machine (Abstract)

N. Sitkoff , Div. of Eng., Brown Univ., Providence, RI, USA
M. Wazlowski , Div. of Eng., Brown Univ., Providence, RI, USA
A. Smith , Div. of Eng., Brown Univ., Providence, RI, USA
H. Silverman , Div. of Eng., Brown Univ., Providence, RI, USA
pp. 0180
Session 8: Applications II

Rapid prototyping of a RISC architecture for implementation in FPGAs (Abstract)

R.D. Meier , Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 0190

FPGA-based transformable computers for fast digital signal processing (Abstract)

H.A. Chow , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
H. Alnuweiri , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
S. Casselman , Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
pp. 0197

Convolution on Splash 2 (Abstract)

N.K. Ratha , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, US
A.K. Jain , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, US
D.T. Rover , Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, US
pp. 0204

Hidden Markov modeling and fuzzy controllers in FPGAs (Abstract)

H. Schmit , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Thomas , Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 0214

Authors Index (PDF)

pp. 0222
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