The Community for Technology Leaders
EUROMICRO Conference (2000)
Maastricht, The Netherlands
Sept. 5, 2000 to Sept. 7, 2000
ISBN: 0-7695-0780-8
TABLE OF CONTENTS
K1 Keynote
K2 Keynote
K3 Keynote

On the Use of Reminder Systems in Healthcare (Abstract)

R. Bindels , University of Maastricht
P. de Clercq , University of Maastricht
A. Hasman , University of Maastricht
pp. 1020
K4 Keynote
K5 Keynote

How to Implement the Future? (Abstract)

C. Verhoef , University of Amsterdam
pp. 1032
A1 Decomposition-based Logic Synthesis

A New State Assignment Method Targeting FPGA Implementations (Abstract)

Aleksander Slusarczyk , Eindhoven University of Technology
Lech Józwiak , Eindhoven University of Technology
pp. 1050

An Improved Column Compatibility Approach for Partition Based Functional Decomposition (Abstract)

Muthukumar Venkatesan , Monash University
Robert Bignall , Monash University in Malaysia
Henry Selvaraj , University of Nevada at Las Vegas
pp. 1067
B1 System Design

A Simulink(c)-Based Approach to System Level Design and Architecture Selection (Abstract)

B. Pino , Universidad de Granada
A. Serra , Politecnico di Torino
L. Lavagno , Universit? di Udine
L.M. Reyneri , Politecnico di Torino
pp. 1076

Behavioral Specification of a Circuit Using SyncCharts: A Case Study (Abstract)

Charles André , University of Nice Sophia-Antipolis
Marie-Agnès Peraldi-Frati , University of Nice Sophia-Antipolis
pp. 1091
C1 Design Validation using Formal Methods

Verification of Designs Containing Black Boxes (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
Wolfgang Günther , Albert-Ludwigs-University
Nicole Drechsler , Albert-Ludwigs-University
pp. 1100

Formal Coverification of Embedded Systems Using Model Checking (Abstract)

Petru Eles , Link?ping University
Luis Alejandro Cortés , Link?ping University
Zebo Peng , Link?ping University
pp. 1106

Can Automatic Design Error Correction be Applied to Large Circuits? (Abstract)

Dirk W. Hoffmann , University of T?bingen
Thomas Kropf , University of T?bingen
pp. 1114

IC Design Validation Using Message Sequence Charts (Abstract)

Sjouke Mauw , Eindhoven University of Technology
Loe Feijs , Eindhoven University of Technology
Tomás Garciá Garciá , Eindhoven University of Technology
Harald Vranken , Philips Research Laboratories
pp. 1122
D1 Technology-Driven Logic Synthesis
E1 New Approaches to Logic Synthesis

Application of Design Style in Evolutionary Multi-Level Networks Synthesis (Abstract)

Joanna Kolodziejczyk , Technical University of Szczecin
Claudio Moraga , Dortmund University
Tadeusz Luba , Warsaw University of Technology
Svetlana Yanushkevich , Technical University of Szczecin
Vlad Shmerko , Technical University of Szczecin
pp. 1156

A Novel Approach to Minimizing the Logic of Combinatorial Multiplexing Circuits in Product-Term-Based Hardware (Abstract)

Orlando Moreira , Philips Research Laboratories and Aveiro University
Bernardo Kastrup , Philips Research Laboratories
pp. 1164

A New Method of Redundancy Addition for Circuit Optimization (Abstract)

V. Saposhnikov , Railway Transportation State University
V. Ocheretnij , University of Potsdam
M. Goessel , University of Potsdam
Vl. Saposhnikov , Railway Transportation State University
pp. 1172
F1 DFT and Testing

Extensive Testing of Floating Point Unit (Abstract)

Janusz Sosnowski , Warsaw University of Technology
Tomasz Bech , Warsaw University of Technology
pp. 1180

Testability of Circuits Derived from Lattice Diagrams (Abstract)

Wolfgang Günther , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
Rolf Drechsler , Albert-Ludwigs-University
pp. 1188

Behavior-Preserving Transformations for Design-for-Test (Abstract)

J.P.M. Voeten , Eindhoven University of Technology
H.P.E. Vranken , Eindhoven University of Technology
pp. 1193
G1 FPGA-Targetted and Non-Binary Logic Design

Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms (Abstract)

José Ignacio Hidalgo , Universidad Complutense de Madrid
Juan Lanchares , Universidad Complutense de Madrid
Roman Hermida , Universidad Complutense de Madrid
pp. 1204

A Parameter to Measure the Efficiency of FPGA Based Logic Synthesis Tools (Abstract)

H. Selvaraj , University of Nevada at Las Vegas
B. Li , University of Nevada at Las Vegas
pp. 1212
H1 High Level Design

Concurrent Control Systems: From Grafcet to VHDL (Abstract)

Fernand Boéri , Universit? de Nice Sophia Antipolis
Frédéric Mallet , Universit? de Nice Sophia Antipolis
Daniel Gaffé , Universit? de Nice Sophia Antipolis
pp. 1230
A2 FPGA-based Processors

FPGA Implementation of Wavelet Packet Transform with Reconfigurable Tree Structure (Abstract)

María A. Trenas , Universidad de M?laga
Juan López , Universidad de M?laga
Emilio L. Zapata , Universidad de M?laga
pp. 1244

Constant Coefficient Multiplication in FPGA Structures (Abstract)

Kazimierz Wiatr , AGH Technical University
Ernest Jamro , AGH Technical University
pp. 1252

FPGA Based Systems with Linear and Non-Linear Signal Processing Capabilities (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul
Denis T. Franco , Universidade Cat?lica de Pelotas
pp. 1260
B2 Memory-Oriented Architectures

Memory Architecture for Parallel Line Drawing Based on Non Incremental Algorithm (Abstract)

Pere Marès Martí , Universitat Polit?cnica de Catalunya
Antonio B. Martínez Velasco , Universitat Polit?cnica de Catalunya
pp. 1266

Scalable Hardware-Algorithm for Mark-Sweep Garbage Collection (Abstract)

Chia-Tien Dan Lo , Illinois Institute of Technology
Witawas Srisa-an , Illinois Institute of Technology
J. Morris Chang , Illinois Institute of Technology
pp. 1274

The Impact of Recent DRAM Architectures on Embedded Systems Performance (Abstract)

Matthias Gries , Swiss Federal Institute of Technology
pp. 1282
C2 Instruction Level Paralellism

Power-Efficient Value Speculation for High-Performance Microprocessors (Abstract)

Rafael Moreno , Universidad Complutense de Madrid
Francisco Tirado , Universidad Complutense de Madrid
Silvia del Pino , Universidad Complutense de Madrid
Luis Piñuel , Universidad Complutense de Madrid
pp. 1292

Techniques for Improving Timing Convergence of Advanced Microprocessors (Abstract)

Paul Kartschoke , IBM Microelectronics Division
Shervin Hojat , IBM Microelectronics Division
pp. 1300

Counter Based Superscalar Instruction Issuing (Abstract)

Ben Juurlink , Delft University of Technology
Stamatis Vassiliadis , Delft University of Technology
Sorin Cotofana , Delft University of Technology
pp. 1307

Influence of High-Level Program Structures on Branch Prediction Accuracy (Abstract)

Afshin Ganjoo , University of Louisiana at Lafayette
Nian-Feng Tzeng , University of Louisiana at Lafayette
pp. 1316
D2 Algorithm-Oriented Architectures

Parallel Architecture for Conversion of NURBS Curves to B?zier Curves (Abstract)

P.N. Mallón , University of Santiago de Compostela
J.D. Bruguera , University of Santiago de Compostela
M. Bóo , University of Santiago de Compostela
pp. 1324

Advanced POC Model-Based Java Instruction Folding Mechanism (Abstract)

Austin Kim , Illinois Institute of Technology
Morris Chang , Illinois Institute of Technology
pp. 1332
E2 Configurable Architectures

The ManArray( Embedded Processor Architecture (Abstract)

Gerald G. Pechanek , Billions of Operations Per Second, Inc.
Stamatis Vassiliadis , Delft University of Technology
pp. 1348

Reliability Analysis of a Self-Repairing Embryonic Machine (Abstract)

Daniel Mange , Swiss Federal Institute of Technology
César Ortega-Sánchez , University of York
Andy Tyrrell , University of York
Gianluca Tempesti , Swiss Federal Institute of Technology
André Stauffer , Swiss Federal Institute of Technology
pp. 1356

Development of Programmable Architecture for Base-Band Processing (Abstract)

Ahmed Hemani , Royal Institute of Technology
Adam Postula , University of Queensland
Simon Leung , University of Queensland
pp. 1362
F2 High-Speed Processing

Designing Competitive Coherence Protocols Taking Advantage of Reuse Information (Abstract)

Julio Sahuquillo , Universidad Polit?cnica de Valencia
Ana Pont , Universidad Polit?cnica de Valencia
pp. 1378

Designing High-Speed Asynchronous Pipelines (Abstract)

Giuseppe Cocorullo , University of Calabria and IRECE-National Council of Research
Stefania Perri , University of Calabria
Pasquale Corsonello , University of Reggio Calabria
pp. 1394

Complex Streamed Instructions: Introduction and Initial Evaluation (Abstract)

Ben Juurlink , Delft University of Technology
Stamatis Vassiliadis , Delft University of Technology
Edwin Hakkennes , Delft University of Technology
pp. 1400
G2 IP and Design Reuse

Parameterized Reusable Component Library Methodology (Abstract)

Rupesh S. Shelar , Silicon Automation Systems
Jagmohan S. Nanaware , Silicon Automation Systems
Sacheendra Nath , Silicon Automation Systems
pp. 1410

Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Tobias Schubert , Albert-Ludwigs-University
Nicole Drechsler , Albert-Ludwigs-University
Elke Mackensen , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
pp. 1425
H2 Hot Topic: System C

Simulation Meets Verification: Checking Temporal Properties in SystemC (Abstract)

Thomas Kropf , University of T?bingen
Jürgen Ruf , University of T?bingen
Dirk W. Hoffmann , University of T?bingen
Wolfgang Rosenstiel , University of T?bingen
pp. 1435
A3 Multimedia Networking (Transmission)

A Fast Method to Optimize Network Resources for Video on Demand Transmission (Abstract)

Joan Vila-Carbó , Dpto. de Inform?tica de Sistemas y Computadores
pp. 1440

On the Use and Calculation of the Hurst Parameter with MPEG Videos Data Traffic (Abstract)

J.C. Cano , Universidad Polit?cnica de Valencia
Pietro Manzoni , Universidad Polit?cnica de Valencia
pp. 1448

A Multimedia Synchronization Protocol for Multicast Groups (Abstract)

Abderrahim Benslimane , Universit? de Technologie de Belfort-Montb?liard
pp. 1456
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