The Community for Technology Leaders
EUROMICRO Conference (1999)
Milan, Italy
Sept. 8, 1999 to Sept. 10, 1999
ISBN: 0-7695-0321-7
TABLE OF CONTENTS
Workshop on Digital System Design: Architectures, Methods and Tools
Keynote
System Architecture Exploration

Exploiting Data Transfer Locality in Memory Mapping (Abstract)

Peeter Ellervee , ESD, KTH-Electrum, Electrum
Ahmed Hemani , ESD, KTH-Electrum, Electrum
Francky Catthoor , IMEC and Katholieke Universiteit Leuven
pp. 1014

Synthesis of Distributed Embedded Systems (Abstract)

Krzysztof Kuchcinski , Link?ping University
pp. 1022
Special Architectures Poster Session

Specialized Processor for Channel Allocation in a Cellular Mobile Network (Abstract)

Ki Leung , The University of Queensland
Adam Postula , The University of Queensland
pp. 1038

Reconfiguration Mechanism for an IP Block Based Interconnection (Abstract)

Kimmo Kuusilinna , Tampere University of Technology
Pasi Liimatainen , Tampere University of Technology
Timo Hämäläinen , Tampere University of Technology
Jukka Saarinen , Tampere University of Technology
pp. 1042

Parallelization of Algorithms for a System of Digital Signal Processors (Abstract)

Mathias Kortke , Dresden University of Technology
Dirk Fimmel , Dresden University of Technology
Renate Merker , Dresden University of Technology
pp. 1046

A Neuro-Fuzzy Real-Time Image Processing System (Abstract)

Claudio Sansoè , Politecnico di Torino
Francesco Gregoretti , Politecnico di Torino
Leonardo M. Reyneri , Politecnico di Torino
pp. 1051

Delft-Java Dynamic Translation (Abstract)

John Glossner , IBM Research and Delft University of Technology
Stamatis Vassiliadis , Delft University of Technology
pp. 1057

A Pipelined Reconfigurable Architecture for Visual-Based Navigation (Abstract)

Jose A. Boluda , Universit?t de Valencia
Fernando Pardo , Universit?t de Valencia
Francisco Blasco , Universit?t de Valencia
Joan Pelechano , Universit?t de Valencia
pp. 1071

Hazard Checking in Pipelined Processor Designs Using Symbolic Model Checking (Abstract)

Jens Schönherr , Fraunhofer Institut f?r Integrierte Schaltungen (IIS), Erlangen, Au?enstelle EAS
Ingo Schreiber , Fraunhofer Institut f?r Integrierte Schaltungen (IIS), Erlangen, Au?enstelle EAS
Eva Fordran , Fraunhofer Institut f?r Integrierte Schaltungen (IIS), Erlangen, Au?enstelle EAS
Bernd Straube , Fraunhofer Institut f?r Integrierte Schaltungen (IIS), Erlangen, Au?enstelle EAS
pp. 1075
Logic Synthesis for FPGAs and CLPDs

Generation of Optimal Universal Logic Modules (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Wolfgang Günther , Albert-Ludwigs-University
pp. 1080
Special Architectures

A Novel Approach for CMOS Parallel Counter Design (Abstract)

Rong Lin , State University of New York at Geneseo
Kevin E. Kerr , Hewlett-Packard Company
Andre S. Botha , Questa Corporation
pp. 1112

A Systolic Library for Solving Matrix Equations (Abstract)

Gloria Martínez , Universitat Jaume I
Germán Fabregat , Universitat Jaume I
Vicente Hernández , Universitat Polit?cnica de Valencia
pp. 1120

The X-MatchLITE FPGA-Based Data Compressor (Abstract)

José Luis Núñez , Loughborough University
Claudia Feregrino , Loughborough University
Simon Jones , Loughborough University
Stephen Bateman , GateField Corporation
pp. 1126

Implementing a Quantitative Model for the "Effective" Signal Processing in the Auditory System on a Dedicated Digital VLSI Hardware (Abstract)

A. Schwarz , University of Hamburg
B. Mertsching , University of Hamburg
M. Brucke , University of Oldenburg
W. Nebel , University of Oldenburg
J. Tschorz , University of Oldenburg
B. Kollmeier , University of Oldenburg
pp. 1133

A Floating Point Vectoring Algorithm Based on Fast Rotations (Abstract)

Kees-Jan Van der Kolk , Delft University of Technology
Ed F.A. Deprettere , Delft University of Technology
Jeong-A Lee , Chosun University
pp. 1140
Logic Synthesis for FPGAs

Logic Restructuring for MUX-Based FPGAs (Abstract)

J.A. Espejo , University Carlos III of Madrid.
L. Entrena , University Carlos III of Madrid.
E. San Millán , University Carlos III of Madrid.
E. Olias , University Carlos III of Madrid.
pp. 1161
CPU and Memory Architectures I

Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention (Abstract)

Song Chen , University of Queensland
Adam Postula , University of Queensland
Lech Jozwiak , Eindhoven University of Technology
pp. 1170
Specification and Modeling

V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration (Abstract)

Asheesh Khare , University of California at Irvine
Nicolae Savoiu , University of California at Irvine
Ashok Halambi , University of California at Irvine
Peter Grun , University of California at Irvine
Nikil Dutt , University of California at Irvine
Alex Nicolau , University of California at Irvine
pp. 1196

A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines (Abstract)

Gregorio Cappuccino , University of Calabria
Giuseppe Cocorullo , University of Calabria and IRECE-National Council of Research
pp. 1204

A Reusable Inner Product Unit for DSP Applications (Abstract)

M.A. Sacristan , Universidad Polit?cnica de Madrid
V. Rodellar , Universidad Polit?cnica de Madrid
A. Diaz , Universidad Polit?cnica de Madrid
V. Garcia , Universidad Polit?cnica de Madrid
P. Gomez , Universidad Polit?cnica de Madrid
pp. 1209
CPU and Memory Architectures Poster Session

A Selective Compressed Memory System by On-Line Data Decompressing (Abstract)

Jang-Soo Lee , Yonsei University
Won-Kee Hong , Yonsei University
Shin-Dug Kim , Yonsei University
pp. 1224

A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs (Abstract)

Øyvind Strøm , Norwegian University of Science and Technology
Audun Klauseie , Norwegian University of Science and Technology
Einar J. Aas , Norwegian University of Science and Technology
pp. 1232

A Segmented Gray Code for Low-Power Microcontroller Address Buses (Abstract)

Rolf Hakenes , University of Saarland
Yiannos Manoli , University of Saarland
pp. 1240

Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications (Abstract)

Alessandro de Gloria , University of Genoa
Paolo Palma , University of Genoa
Mauro Olivieri , University of Rome "La Sapienza"
pp. 1244

Context-Switching Techniques for Decoupled Multithreaded Processors (Abstract)

Jochen Kreuzinger , University of Karlsruhe
Theo Ungerer , University of Karlsruhe
pp. 1248
Testing and Verification

Self-Testing of S-Compatible Test Units in User-Programmed FPGAs (Abstract)

Pawel Tomaszewicz , Warsaw University of Technology
Andrzej Krasniewski , Warsaw University of Technology
pp. 1254

Application-Dependent Testing of FPGA Delay Faults (Abstract)

Andrzej Krasniewski , Warsaw University of Technology
pp. 1260

Language Based Design Verification with Semantic Analysis (Abstract)

George Economakos , National Technical University of Athens
George Papakonstantinou , National Technical University of Athens
pp. 1268
Logic and High Level Synthesis Poster Session

Results in Comparing Innovative Placement Heuristics (Abstract)

Reinhard Rauscher , University of Hamburg
Dieter Klawan , University of Hamburg
pp. 1282

The Universal Algorithm for Fitting Targeted to Complex Programmable Logic Devices (Abstract)

V. Solovjev , Technical University of Bialystok
M. Chyzy , Technical University of Bialystok
pp. 1286
Embedded System Optimization and Prototyping

An Improved Scheduling Technique for Time-Triggered Embedded Systems (Abstract)

Paul Pop , Link?ping University
Petru Eles , Link?ping University
Zebo Peng , Link?ping University
pp. 1303

Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems (Abstract)

Luca Benini , Universit? di Bologna
Alberto Macii , Politecnico di Torino
Enrico Macii , Politecnico di Torino
Massimo Poncino , Politecnico di Torino
pp. 1311

A Prototyping Method of Embedded Real Time Systems for Signal Processing Applications (Abstract)

Luc Bianco , I3S, Universit? de Nice Sophia Antipolis
Michel Auguin , I3S, Universit? de Nice Sophia Antipolis
Alain Pegatoquet , I3S, Universit? de Nice Sophia Antipolis and VLSI Technology
pp. 1318
Reconfigurable Architectures

Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine (Abstract)

Torrey Lewis , Portland State University
Marek Perkowski , Portland State University
Lech Jozwiak , Eindhoven University of Technology
pp. 1326

Design of a Flexible Coprocessor Unit (Abstract)

Till Harbaum , Technical University of Braunschweig
Detlef Meier , Technical University of Braunschweig
Matthias Prinke , Technical University of Braunschweig
Martina Zitterbart , Technical University of Braunschweig
pp. 1335

A Tool for Teaching and Research on Computer Architecture and Reconfigurable Systems (Abstract)

Christof Teuscher , Swiss Federal Institute of Technology
Jacques-Olivier Haenni , Swiss Federal Institute of Technology
Hector Fabio Restrepo , Swiss Federal Institute of Technology
Eduardo Sanchez , Swiss Federal Institute of Technology
Francisco J. Gómez , Universidad Autonoma de Madrid
pp. 1343
Decision Diagrams, Decomposition and Optimization

Generic Implementation of DD Packages in MVL (Abstract)

Rolf Drechsler , Albert-Ludwigs-University
Dragan Jankovic , Albert-Ludwigs-University
Radomir S. Stankovic , Albert-Ludwigs-University
pp. 1352

Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates (Abstract)

Rafal Rzechowski , Warsaw University of Technology
Tadeusz Luba , Warsaw University of Technology
Lech Jozwiak , Eindhoven University of Technology
pp. 1368
Specification and Modeling Poster Session

An Interactive Modeling and Generation Tool for the Design of Hw/Sw Systems (Abstract)

F. Muller , IRESTE University of Nantes
J.P. Calvez , IRESTE University of Nantes
D. Heller , IRESTE University of Nantes
O. Pasquier , IRESTE University of Nantes
pp. 1382

Unified Modeling Graph for Specifying and Synthesizing Chip-Level Interfaces (Abstract)

Young Moo Lee , Korea Advanced Institute of Science and Technology
Kyu Ho Park , Korea Advanced Institute of Science and Technology
pp. 1388

A Message-Passing Communication Scheme for System Specification (Abstract)

Francesco Curatelli , D.I.B.E. - University of Genova
Leonardo Mangeruca , D.I.B.E. - University of Genova
Marco Chirico , D.I.B.E. - University of Genova
pp. 1390

Knowledge Based Specification and Modeling of Embedded Systems (Abstract)

M. Sporer , Chemnitz University of Technology
K. Agsteiner , Chemnitz University of Technology
D. Monjau , Chemnitz University of Technology
M. Schwaar , Chemnitz University of Technology
pp. 1398

Modeling Bit Multiplication Blocks for DSP Applications Using VHDL (Abstract)

Sýddýka Berna Örs , Istanbul Technical University
Ahmet Dervisoglu , Istanbul Technical University
pp. 1402

Application of FHM-Based Design Method to Scalable 2-D DCT Processor (Abstract)

Eiichirou Shigehara , Osaka University
Yoshinori Takeuchi , Osaka University
Masaharu Imai , Osaka University
Tsutomu Kimura , Toyota College of Technology
pp. 1406
CPU and Memory Architectures 2

A New Destage Algorithm for Disk Cache: DOME (Abstract)

Marina Alonso , Universidad Polit?cnica de Valencia
Vicente Santonja , Universidad Polit?cnica de Valencia
pp. 1416

The Filter Cache: A Run-Time Cache Management Approach1 (Abstract)

Julio Sahuquillo , Universidad Polit?cnica de Valencia
Ana Pont , Universidad Polit?cnica de Valencia
pp. 1424

An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism (Abstract)

Ryotaro Kobayashi , Nagoya University
Yukihiro Ogawa , Nagoya University
Hideki Ando , Nagoya University
Toshio Shimada , Nagoya University
Mitsuaki Iwata , Mihara Machinery Works, Mitsubishi Heavy Industries, Ltd.
pp. 1432

Extending Correlation in Branch Prediction Schemes (Abstract)

Lucian N. Vintan , University "L. Blaga"
Colin. Egan , University of Hertfordshire
pp. 1441

Enhancing Security in the Memory Management Unit (Abstract)

Tanguy Gilmont , Universit? Catholique de Louvain
Jean-Didier Legat , Universit? Catholique de Louvain
Jean-Jacques Quisquater , Universit? Catholique de Louvain
pp. 1449
System Synthesis and Validation Poster Session

Software Synthesis for System Level Design Using Process Execution Trees (Abstract)

L.J. Van Bokhoven , Eindhoven University of Technology
J.P.M. Voeten , Eindhoven University of Technology
M.C.W. Geilen , Eindhoven University of Technology
pp. 1463

Evaluation of Design Space Exploration Strategies (Abstract)

Francisco Moya , Universidad de Castilla-La Mancha
Juan C. López , Universidad de Castilla-La Mancha
José M. Moya , Universidad Polit?cnica de Madrid
pp. 1472

A Method for Accelerating Test Environments (Abstract)

Matthias Bauer , Infineon Technologies
Wolfgang Ecker , Infineon Technologies
Renate Henftling , Infineon Technologies
Andreas Zinn , Infineon Technologies
pp. 1477

Tracing Fault Effects in System Environment (Abstract)

Janusz Sosnowski , Warsaw University of Technology
Piotr Gawkowski , Warsaw University of Technology
pp. 1481

A Hardware/Software Cosimulation Environment for DSP Applications (Abstract)

Christian Kreiner , Technical University of Graz
Christian Steger , Technical University of Graz
Reinhold Weiss , Technical University of Graz
pp. 1492

System Level Models for Real-Time Communication (Abstract)

P.H.A. Van der Putten , Eindhoven University of Technology
J.P.M. Voeten , Eindhoven University of Technology
M.C.W. Geilen , Eindhoven University of Technology
M.P.J. Stevens , Eindhoven University of Technology
pp. 1496
High Level Synthesis

A Unified Algorithm for Mutual Exclusiveness Identification (Abstract)

O. Peñalba , Universidad Complutense de Madrid
J. M. Mendías , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 1504

VHDL Description and High-Level Synthesis of an ATM Layer Circuit (Abstract)

Walter Lange , Universit?t T?bingen
Wolfgang Rosenstiel , Universit?t T?bingen
pp. 1519
91 ms
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