The Community for Technology Leaders
EUROMICRO Conference (1998)
Västerås, Sweden
Aug. 25, 1998 to Aug. 27, 1998
ISSN: 1089-6503
ISBN: 0-8186-8646-4
Workshop A. Digital Systems Design
Keynote Speech

Keynote (PDF)

pp. null
Session A.1: Combinational Logic Design

Solving Synthesis Problems with Genetic Algorithms (Abstract)

Niek Ederveen , Eindhoven University of Technology
Lech Jóźwiak , Eindhoven University of Technology
Adam Postuła , University of Queensland
pp. 10001

Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measures (Abstract)

Artur Chojnacki , Eindhoven University of Technology
Lech Jóźwiak , Eindhoven University of Technology
Tadeusz Łuba , Warsaw University of Technology
Mariusz Rawski , Warsaw University of Technology
pp. 10008

An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables (Abstract)

Lech Jóźwiak , Technical University of Eindhoven
Marek Perkowski , Portland State University
Michael Burns , Portland State University
pp. 10016
Session A.2: Poster Presentation

Design Correctness of Digital Systems (Abstract)

Corrie Huijs , University of Twente
pp. 10030

Specification of Exception Handling in Grammar-Based Hardware Synthesis (Abstract)

Anshul Kumar , Indian Institute of Technology
Ahmed Hemani , Royal Institute of Technology
Johnny ?berg , Royal Institute of Technology
pp. 10038

Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a Chip (Abstract)

Fr?d?ric P?trot , Universit? Pierre et Marie Curie
Denis Hommais , Universit? Pierre et Marie Curie
pp. 10051

Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces (Abstract)

Mattias O?Nils , Royal Institute of Technology
Axel Jantsch , Royal Institute of Technology
Johnny ?berg , Royal Institute of Technology
pp. 10055

A Uni.ed Component Modeling Approach for Performance Estimation in Hardware/Software Codesign (Abstract)

Jan Madsen , Technical University of Denmark
Jesper Grode , Technical University of Denmark
pp. 10065
Session A.3: High-Level Synthesis

Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment (Abstract)

George Economakos , National Technical University of Athens
George Papakonstantinou , National Technical University of Athens
pp. 10091

Register Allocation with Simultaneous BIST Intrusion (Abstract)

J. F. Tirado , Universidad Complutense de Madrid
K. Olcoz , Universidad Complutense de Madrid
pp. 10099
Session A.4: Custom Computing Machines

Automated Synthesis of Interleaved Memory Systems for Custom Computing Machines (Abstract)

Song Chen , University of Queensland
Lech Jozwiak , Eindhoven University of Technology
David Abramson , Monash University
Adam Postula , University of Queensland
pp. 10115

Image Convolution on FPGAs: The Implementation of a Multi-FPGA FIFO Structure (Abstract)

Andrea Prati , Universit? di Modena
Arrigo Benedetti , Universit? di Modena and California Institute of Technology
Nello Scarabottolo , Universit? di Modena
pp. 10123

Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory (Abstract)

Montserrat Bóoand , University of Santiago de Compostela
Javier D. Bruguera , University of Santiago de Compostela
Roberto R. Osorio , University of Santiago de Compostela
pp. 10139
Session A.5: System Level Design

Hardware Architecture Modelling Using an Object-Oriented Method (Abstract)

Fr?d?ric Mallett , Universit? de Nice-Sophia Antipolis
Jean-Fran?ois Duboc , VLSI Technology Inc.
Fernand Boeri , Universit? de Nice-Sophia Antipolis
pp. 10147

System Level Modelling for Hardware/Software Systems (Abstract)

M.C.W. Geilen , Eindhoven University of Technology
J.P.M. Voeten , Eindhoven University of Technology
M.P.J. Stevens , Eindhoven University of Technology
P.H.A. van der Putten , Eindhoven University of Technology
pp. 10154

Hardware-Softw are Run-Time Systems and Robotics: A Case Study (Abstract)

Oussama Khatib , Stanford University
Giovanni De Micheli , Stanford University
Diego Ruspini , Stanford University
Vincent John Mooney III , Georgia Institute of Technology
pp. 10162

Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems (Abstract)

Paul Pop , Link?ping University
Petru Eles , Link?ping University
Krzysztof Kuchcinski , Link?ping University
Alexa Doboli , University of Cincinnati
Zebo Peng , Link?ping University
pp. 10168
Session A.6: Poster Presentations

Minimization of Algorithmic State Machines (Abstract)

Samary Baranov , Center for Technological Education
pp. 10176

Experimental Evaluation of Pseudorandom Test Effectiveness (Abstract)

J. Sosnowski , Warsaw University of Technology
pp. 10184

Entropy-Based Design of Low Power FSMs (Abstract)

Lilia Kashirova , Tallinn Technical University
Olga Tveretina , Kharkov Politechnical University
pp. 10188

RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing (Abstract)

Juan de Vicente , E.T.S.I.A.N.
Juan Lanchares , Universidad Complutense de Madrid
Rom? Hermida , Universidad Complutense de Madrid
pp. 10192

Design of Virtual Digital Controllers Based on Dynamically Reconfigurable FPGAs (Abstract)

Arnaldo Oliveira , Aveiro University
Konstantin Kondratjuk , Aveiro University
Nuno Lau , Aveiro University
Ricardo Sal Monteiro , Aveiro University
Valery Sklyarov , Aveiro University
Andreia Melo , Aveiro University
pp. 10200

The Impact of Area Optimization for the Power Consumption of Controllers (Abstract)

H.-Ch. Dahmen , The German National Research Center for Information Technology
U. Gl?ser , The German National Research Center for Information Technology
pp. 10204

Extending a Monoprocessor Real-Time System in a Multiprocessing Environment, DSP-Based (Abstract)

M. Bartolucci , Chimera Collaboration
S. Femino , Chimera Collaboration
M. Geraci , Chimera Collaboration
S. Cavallaro , Chimera Collaboration
M. Papa , Chimera Collaboration
G. Manfredi , Chimera Collaboration
P. Guazzoni , Chimera Collaboration
A. Pagano , Chimera Collaboration
G. Savino , Chimera Collaboration
L. Sperduto , Chimera Collaboration
S. Lo Nigro , Chimera Collaboration
G. Cardella , Chimera Collaboration
E. De Filippo , Chimera Collaboration
F. Porto , Chimera Collaboration
L. Zetta , Chimera Collaboration
C. Sutera , Chimera Collaboration
S. Aiello , Chimera Collaboration
S. Sambataro , Chimera Collaboration
G. Lanzano , Chimera Collaboration
M. Iacono Manno , Chimera Collaboration
G. Politi , Chimera Collaboration
G. Lanzalone , Chimera Collaboration
S. Pirrone , Chimera Collaboration
C. Garusi , Chimera Collaboration
F. Giustolisi , Chimera Collaboration
A. Anzalone , Chimera Collaboration
F. Rizzo , Chimera Collaboration
pp. 10208

A Useful Micropipeline Architecture to Implement DSP Algorithms (Abstract)

Juraj Povazanec , Chinese University of Hong Kong
Cheong-fat Chan , Chinese University of Hong Kong
Chiu-sing Choy , Chinese University of Hong Kong
Tin-chak Pang , Chinese University of Hong Kong
pp. 10212
Session A.7: Applications

Control System for a Low Energy Particle Detector (Abstract)

L. del Peral , Universidad de Alcal?
J. Medina , Universidad de Alcal?
J. Rodr?guez-Pacheco , Universidad de Alcal?
E. Bronchalo , Universidad de Alcal?
S. S?nchez , Universidad de Alcal?
M. Carbajo , Universidad de Alcal?
D. Meziat , Universidad de Alcal?
pp. 10216

DELFT-JAVA Link Translation Buffer (Abstract)

Stamatis Vassiliadis , Delft University of Technology
John Glossner , Lucent / Bell Labs and Delft University of Technology
pp. 10221
Session A.8: Real-Time Embedded Systems

Rate Assignment for Embedded Reactive Real-Time Systems (Abstract)

Youngsoo Shin , Seoul National University
Kiyoung Choi , Seoul National University
pp. 10237

Hardware to Software Migration with Real-Time Thread Integration (Abstract)

Alexander G. Dean , Carnegie Mellon University
John Paul Shen , Carnegie Mellon University
pp. 10243
Session A.9: Seqential Logic Synthesis

Design of Self-Synchronized Component FSMs for Self-Timed Systems (Abstract)

Lech Jozwiak , Technical University of Eindhoven
Loc Bao Nguen , Intel Supercomputer
Marek Perkowski , Portland State University
pp. 10253

Multi-Criterial State Assignment for Low Power FSM Design (Abstract)

Manfred Koegst , Fraunhofer-Institut Integrierte Schaltungen
Steffen R? , Fraunhofer-Institut Integrierte Schaltungen
Klaus Feske , Fraunhofer-Institut Integrierte Schaltungen
G? Franke , Hochschule f?r Technik und Wirtschaft Dresden
pp. 10261

A New Approach to And/Or/Exor Factorization for Regular Arrays (Abstract)

Ning Song , Portland State University
Marek Perkowski , Portland State University
pp. 10269
Session A.10: Processor and Parallel Architectures

On the Design Complexity of the Issue Logic of Superscalar Machines (Abstract)

Sorin Cotofana , Delft University of Technology
Stamatis Vassiliadis , Delft University of Technology
pp. 10277

The Latency Hiding Effectiveness of Decoupled Access/Execute Processors (Abstract)

Antonio Gonz?lez , Universitat Polit?cnica de Catalunya
Joan-Manuel Parcerisa , Universitat Polit?cnica de Catalunya
pp. 10293

Revolver: A High-Performance MIMD Architecture for Collision Free Computing (Abstract)

Johnny ?berg , Royal Institute of Technology
Peeter Ellervee , Royal Institute of Technology
pp. 10301
Session A.11: Poster Presentations

A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Process (Abstract)

J. Septi? , Universidad Complutense
J. A. Maestro , Universidad Complutense
D. Mozos , Universidad Complutense
pp. 10309

Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis (Abstract)

Rajesh K. Bawa , Universit? Pierre et Marie Curie
Ludovic Jacomme , Universit? Pierre et Marie Curie
Fr?d?ric P?trot , Universit? Pierre et Marie Curie
pp. 10317

Data Speculative Multithreaded Architecture (Abstract)

Antonio Gonz?lez , Universitat Polit?cnica de Catalunya
Pedro Marcuello , Universitat Polit?cnica de Catalunya
pp. 10321

The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture (Abstract)

Gordon Steven , University of Hertfordshire
Daniel Tate , University of Hertfordshire
Paul Findlay , University of Hertfordshire
pp. 10325

Impact of Reducing Miss Write Latencies in Multiprocessors with Two Level Cache (Abstract)

Ana Pont , Universidad Polit?cnica de Valencia
Julio Sahuquillo , Universidad Polit?cnica de Valencia
pp. 10333

Efficient High-Speed CMOS Design by Layout Based Schematic Method (Abstract)

Christer Svensson , Linköping University
Fenghao Mu , Linköping University
pp. 10337

A Miniature Serial-Data SIMD Architecture (Abstract)

Per Larsson-Edefors , Link?ping University
pp. 10341
Session A.12: High-Level Synthesis II

Design of Control Dominated Hardware Based on Formal Methods (Abstract)

Werner Grass , Universität Passau
Christine Sontheim , Universität Passau
Stefan Lenk , Universität Passau
pp. 10357

A Method for Mapping DSP Algorithms into Application Specific Structures (Abstract)

Juri Kanevski , Technical University of Koszalin
Oleg Maslennikov , Technical University of Koszalin
Anatoli Sergyienko , National Technical University of Ukraine
Roman Wyrzykowski , Technical University of Czestochowa
pp. 10365
Workshop B. Dependable Computing Systems
Session B.1: Masking Techniques

Simulation of a Component-Oriented Voter Library for Dependable Control Applications (Abstract)

J.M. Bass , University of Sheffield
G. Latif-Shabgahi , University of Sheffield
S. Bennett , University of Sheffield
pp. 10372

The EFTOS Voting Farm: A Software Tool for Fault Masking in Message Passing Parallel Environments (Abstract)

Geert Deconinck , Katholieke Universiteit Leuven
Rudy Lauwereins , Katholieke Universiteit Leuven
Vincenzo De Florio , Katholieke Universiteit Leuven
pp. 10379

Generating Multiple Diverse Software Versions with Genetic Programming (Abstract)

Robert Feldt , Chalmers University of Technology
pp. 10387
Session B.2: Recovery Techniques

An Experimental Study about Diskless Checkpointing (Abstract)

Jo?o Gabriel Silva , Universidade de Coimbra - POLO II
Lu?s M. Silva , Universidade de Coimbra - POLO II
pp. 10395

Dynamic Acceptance Tests for Complex Controllers (Abstract)

T. Clarke , University of York
R. Stroph , University of York
pp. 10411
Session B.3: Fault Injection, Diagnosis and Debugging

Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System (Abstract)

P. J. Gil , Universidad Polit?cnica de Valencia
D. Gil , Universidad Polit?cnica de Valencia
J. V. Busquets , Universidad Polit?cnica de Valencia
J. C. Baraza , Universidad Polit?cnica de Valencia
pp. 10418

On-the-Fly Model Checking of Program Runs for Automated Debugging (Abstract)

M. Frey , Technische Universität München
B.-H. Schlingloff , Universität Bremen
pp. 10426
Session B.4: Development Approaches

On the Effectiveness of Slicing Hierarchical State Machines: A Case Study (Abstract)

Jeffrey M. Thompson , University of Minnesota
Michael W. Whalen , University of Minnesota
Mats P.E. Heimdahl , University of Minnesota
pp. 10435

Engineering Safe, Real-Time Distributed Control Systems (Abstract)

Colin Chambers , University of Sheffield
Peter Croll , University of Sheffield
Naoshi Uchihira , University of Sheffield
Chris Rudram , University of Sheffield
pp. 10445

Towards Standard-Based Specification and Design of Embedded Real-Time Systems (Abstract)

Roman Gumzej , University of Maribor
Domen Verber , University of Maribor
Wolfgang A. Halang , Fern Universität Hagen
Matjaž Colnarič , University of Maribor
pp. 10453
Session B.5: Fault Treatment

A 32-Bit Risc Processor with Concurrent Error Detection (Abstract)

G. Russell , University of Newcastle
A. Maamar , University of Newcastle
pp. 10461

An Experimental Investigation of Message Latencies in the Totem Protocol in the Presence of Faults (Abstract)

Lars Küttner , Humboldt-Universität zu Berlin
Matthias Werner , Humboldt-Universität zu Berlin
Holger Karl , Humboldt-Universität zu Berlin
pp. 10468

Approaches for Scheduling of Triggered Transactions in Real-Time Active Database Systems (Abstract)

Tony S.H. Lee , City University of Hong Kong
Kam-yiu Lam , City University of Hong Kong
pp. 10476
96 ms
(Ver 3.1 (10032016))