The Community for Technology Leaders
EUROMICRO Conference (1996)
Prague, Czech Republic
Sept. 2, 1996 to Sept. 5, 1996
ISBN: 0-8186-7487-3
TABLE OF CONTENTS

Reviewers (PDF)

pp. xix
Session Al : System-Level Design

Quality-Driven Decision Making Methodology for System-Level Design (Abstract)

S.A. Ong , Digitial Syst. Group, Eindhoven Univ. of Technol., Netherlands
L. Jozwiak , Digitial Syst. Group, Eindhoven Univ. of Technol., Netherlands
pp. 0008

Behaviour-Preserving Transformations in SHE: A Formal Approach to Architecture Design (Abstract)

J.P.M. Voeten , Sect. of Digital Inf. Syst., Eindhoven Univ. of Technol., Netherlands
P.H.A. van der Putten , Sect. of Digital Inf. Syst., Eindhoven Univ. of Technol., Netherlands
M.P.J. Stevens , Sect. of Digital Inf. Syst., Eindhoven Univ. of Technol., Netherlands
pp. 0019

Considering Test Economics in the Process of Hardware/Software Partitioning (Abstract)

Y. Le-Traon , LSR-IMAG, Grenoble, France
G. Al-Hayek , LSR-IMAG, Grenoble, France
C. Robach , LSR-IMAG, Grenoble, France
pp. 0028
Session A2: Multiprocessor Architectures

Increasing the Effective Memory Bandwidth in Multivector Processors (Abstract)

J.M. Llaberia , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
A.M. del Corral , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 0038

Implementation of Processor Cells for Array Algorithms on FPGAs (Abstract)

I. Erenyi , KFKI Res. Inst. for Meas. & Comput. Tech., Budapest, Hungary
I. Vassanyi , KFKI Res. Inst. for Meas. & Comput. Tech., Budapest, Hungary
pp. 0046

Mapping of Neural Networks onto Data Flow Graphs (Abstract)

R. Moore , Tech. Inf., J.W. Goethe Univ., Frankfurt, Germany
K. Waldeschmidt , Tech. Inf., J.W. Goethe Univ., Frankfurt, Germany
A.C. Yuceturk , Tech. Inf., J.W. Goethe Univ., Frankfurt, Germany
B. Klauer , Tech. Inf., J.W. Goethe Univ., Frankfurt, Germany
S. Zickenheiner , Tech. Inf., J.W. Goethe Univ., Frankfurt, Germany
pp. 0051
Session A3: Real Time

Real Time (PDF)

pp. 0059

A Comprehensive Approach in Performance Evaluation for Modern Real-Time Operating Systems (Abstract)

A. Vina , Open Real-Time Syst. Center, Univ. de La Coruna, Spain
A. Garcia-Martinez , Open Real-Time Syst. Center, Univ. de La Coruna, Spain
J.F. Conde , Open Real-Time Syst. Center, Univ. de La Coruna, Spain
pp. 0061

An Algorithm for Scheduling Prioritized Tasks in a Hard Real-Time Environment (Abstract)

J. Etkin , GTE Labs. Inc., Waltham, MA, USA
J. Fridman , GTE Labs. Inc., Waltham, MA, USA
pp. 0069

A Formal Design and Implementation Method for Real-Time Embedded Systems (Abstract)

A. Robson , Dept. of Comput., Univ. of Northumbria, Newcastle, UK
S. Bradley , Dept. of Comput., Univ. of Northumbria, Newcastle, UK
S. Hawkes , Dept. of Comput., Univ. of Northumbria, Newcastle, UK
D. Kendall , Dept. of Comput., Univ. of Northumbria, Newcastle, UK
W. Henderson , Dept. of Comput., Univ. of Northumbria, Newcastle, UK
pp. 0077
Session Bl: Design Methodologies and Tools

A Design Assistant for Scheduling of Design Decisions (Abstract)

R. Rauscher , Dept. of Comput. Sci., Hamburg Univ., Germany
pp. 0088

A Novel Circuit Extraction Tool Based on X-Spans and Y-Spans (Abstract)

C.E.T. Oliveira , Nucleo de Computacao Electronica, Univ. Federal do Rio de Janeiro, Brazil
J.M.S. Alcantara , Nucleo de Computacao Electronica, Univ. Federal do Rio de Janeiro, Brazil
M.L. Anido , Nucleo de Computacao Electronica, Univ. Federal do Rio de Janeiro, Brazil
pp. 0096

Automating System-Level Design: From Specification to Architecture (Abstract)

K. Agsteiner , Dept. of Comput. Sci., Univ. of Technol. Chemnitz-Zwickau, Germany
D. Monjau , Dept. of Comput. Sci., Univ. of Technol. Chemnitz-Zwickau, Germany
S. Schulze , Dept. of Comput. Sci., Univ. of Technol. Chemnitz-Zwickau, Germany
pp. 0104
Session B2: Optimization

Optimization (PDF)

pp. 0112

Effective SIMD Code Generation for the High-Level Declarative Data-Parallel Language 8 1/2 (Abstract)

O. Michel , Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France
D. De Vito , Lab. de Recherche en Inf., Univ. de Paris-Sud, Orsay, France
pp. 0114
Session B3: Development of Control Systems

A Macro Expansion Approach to Embedded Processor Code Generation (Abstract)

E. Lassila , Digital Syst. Lab., Helsinki Univ. of Technol., Espoo, Finland
pp. 0136

Functional Validation of Fault-Tolerant Asynchronous Algorithms (Abstract)

P. Smrha , Dept. of Comput. Sci., Czech Tech. Univ., Prague, Czech Republic
S. Racek , Dept. of Comput. Sci., Czech Tech. Univ., Prague, Czech Republic
J. Hlavicka , Dept. of Comput. Sci., Czech Tech. Univ., Prague, Czech Republic
pp. 0143

Software Engineering in Control Using Objects and Services (Abstract)

T. Doersam , Inst. for Microcomput. & Autom., Karlsruhe Univ., Germany
O. Hammerschmidt , Inst. for Microcomput. & Autom., Karlsruhe Univ., Germany
pp. 0158
Session C1: Formal Methods for Hardware Design

A Semantic Model of VHDL for Validating Rewriting Algebras (Abstract)

S.L. Pandey , Comput. Archit. Design Lab., Cincinnati Univ., OH, USA
K.R. Subramanian , Comput. Archit. Design Lab., Cincinnati Univ., OH, USA
P.A. Wilsey , Comput. Archit. Design Lab., Cincinnati Univ., OH, USA
pp. 0167

A Graph Rewriting Approach for Transformational Design of Digital Systems (Abstract)

C. Huijs , Twente Univ., Enschede, Netherlands
pp. 0177

Reachability and Timing Analysis in Data Flow Networks: A Case Study (Abstract)

I. Majzik , Dept. of Meas. & Instrum. Eng., Tech. Univ. Budapest, Hungary
A. Bondavalli , Dept. of Meas. & Instrum. Eng., Tech. Univ. Budapest, Hungary
L. Simoncini , Dept. of Meas. & Instrum. Eng., Tech. Univ. Budapest, Hungary
G. Csertan , Dept. of Meas. & Instrum. Eng., Tech. Univ. Budapest, Hungary
B. Antal , Dept. of Meas. & Instrum. Eng., Tech. Univ. Budapest, Hungary
pp. 0193
Session C2: Performance Engineering

Efficient Simulation of Multiprocessors through Finite State Machines (Abstract)

C. Siegelin , Dept. Inf., Ecole Nat. Superieure des Telecommun., Paris, France
C. O'Donnell , Dept. Inf., Ecole Nat. Superieure des Telecommun., Paris, France
U. Finger , Dept. Inf., Ecole Nat. Superieure des Telecommun., Paris, France
pp. 0202

A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors (Abstract)

R. Giorgi , Dipartimento di Ingegneria dell'Inf., Pisa Univ., Italy
L. Ricciardi , Dipartimento di Ingegneria dell'Inf., Pisa Univ., Italy
C.A. Prete , Dipartimento di Ingegneria dell'Inf., Pisa Univ., Italy
G. Prina , Dipartimento di Ingegneria dell'Inf., Pisa Univ., Italy
pp. 0207

A Novel Approach to Improve the Performance of Interconnection Networks with Hot - Spots (Abstract)

A. Flores , Dept. de Inf. y Sistemas, Murcia Univ., Spain
J.M. Garcia , Dept. de Inf. y Sistemas, Murcia Univ., Spain
pp. 0215

A Load Balancing System for Windows NT Networks (Abstract)

A. Kieda , Inst. of Control & Syst. Eng., Tech. Univ. Wroclaw, Poland
L. Borzemski , Inst. of Control & Syst. Eng., Tech. Univ. Wroclaw, Poland
pp. 0223
Session C3: Usability Engineering

A General Framework for Positioning, Evaluating and Selecting the New Generation of Development Tools (Abstract)

S. Poelmans , Dept. of Appl. Econ. Sci., Katholieke Univ., Leuven, Belgium
J. Vanthienen , Dept. of Appl. Econ. Sci., Katholieke Univ., Leuven, Belgium
pp. 0233

A Multi-Agent Environment for User Interface Design (Abstract)

B.M. Daltrini , Sch. of Electr. Eng., State Univ. of Campinas, Brazil
C.I.S. Arias , Sch. of Electr. Eng., State Univ. of Campinas, Brazil
pp. 0242

Separating Application Functionality from the User Interface in a Distributed Environment (Abstract)

N. Dlodlo , Sch. of Comput. & Math. Sci., Liverpool John Moores Univ., UK
C. Bamford , Sch. of Comput. & Math. Sci., Liverpool John Moores Univ., UK
pp. 0248
Session D1: Logic Synthesis

Logic Synthesis (PDF)

pp. 0257

Results Given by a New Evaluation System for Placement and Routing Heuristics (Abstract)

D. Klawan , Dept. of Comput. Sci., Hamburg Univ., Germany
H.-J. Bandelt , Dept. of Comput. Sci., Hamburg Univ., Germany
R. Rauscher , Dept. of Comput. Sci., Hamburg Univ., Germany
pp. 0259

A System for Heuristic Modifications on PLA - Specifications (Abstract)

A. Krause , Dept. of Comput. Sci., Hamburg Univ., Germany
R. Rauscher , Dept. of Comput. Sci., Hamburg Univ., Germany
pp. 0267

Retiming for Circuits with Enable Registers (Abstract)

H.-G. Martin , Dept. EAS Dresden, FhG IIS Erlangen, Dresden, Germany
pp. 0275
Session D2: Fault Tolerance

Fault Tolerance (PDF)

pp. 0282

Transparency in a Replicated Network File System (Abstract)

Shang-Rong Tsai , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Charles Changli Chin , Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 0285

Recovery Blocks and Algorithm-Based Fault Tolerance (Abstract)

A.M. Tyrrell , Dept. of Electron., York Univ., UK
pp. 0292
Session D3: Specification and Validation

Communication Mechanism Independent Protocol Specification Based on CSP: A Case Study (Abstract)

Yong Sun , Dept. of Comput. Sci., Queen's Univ., Belfast, UK
Hongji Yang , Dept. of Comput. Sci., Queen's Univ., Belfast, UK
pp. 0303

Software Monitoring and Debugging Using Compressed Signature Sequences (Abstract)

I. Majzik , Dept. of Meas. & Instrum. Eng., Tech. Univ. Budapest, Hungary
pp. 0311

Preliminary Analysis Cycle for B-Method Software Development (Abstract)

S. Taouil-Traverson , SNCF, Paris, France
S. Vignes , SNCF, Paris, France
pp. 0319
Session E1: Testing

Testing (PDF)

pp. 0327

Pseudorandom versus Deterministic Testing of Intel 80x86 Processors (Abstract)

A. Kusmierczyk , Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
J. Sosnowski , Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
pp. 0329

On the Adequacy of Deriving Hardware Test Data from the Behavioral Specification (Abstract)

C. Robach , LSR, IMAG, Grenoble, France
G. Al Hayek , LSR, IMAG, Grenoble, France
pp. 0337

DELFIM: Error Detection by Thin Memory Protection (Abstract)

J.G. Silva , Inst. Superior de Engenharia de Coimbra, Portugal
J.C. Cunha , Inst. Superior de Engenharia de Coimbra, Portugal
pp. 0343

SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern Generation (Abstract)

F. Fummi , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
L. Guerrazzi , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
R. Bevacqua , Dipartimento di Elettronica e Inf., Politecnico di Milano, Italy
pp. 0351
Session E2: Dependable Systems

N-Version Programming: A Unified Modeling Approach (Abstract)

K. Goseva-Popstojanova , Dept. of Comput. Sci., fac. of Electr. Eng., Skopje, Macedonia
A. Grnarov , Dept. of Comput. Sci., fac. of Electr. Eng., Skopje, Macedonia
pp. 0363

Performance Evaluation of Testing Strategies in Parallel Systems (Abstract)

F. Chevassu , LSR, IMAG, Grenoble, France
O. Benkahla , LSR, IMAG, Grenoble, France
C. Robach , LSR, IMAG, Grenoble, France
B. Remy , LSR, IMAG, Grenoble, France
pp. 0371

Effective Approximate Fault Diagnosis of Systems with Inhomogeneous Test Invalidation (Abstract)

T. Bartha , Dept. of Meas. & Instrum. Eng., Tech. Univ. Budapest, Hungary
pp. 0379
Session E3: High-Speed Networks

Performance Analysis of Packet Switching Interconnection Networks with Finite Buffers (Abstract)

A. Grnarov , Dept. of Comput. Sci., Univ. St. Kiril i Metodij, Skopje, Macedonia
A. Tentov , Dept. of Comput. Sci., Univ. St. Kiril i Metodij, Skopje, Macedonia
pp. 0390

Multicast Routing Algorithms for Manhattan Street Network (Abstract)

Chongsang Kim , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Hoyoung Hwang , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Yanghee Choi , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
Hyoungjun Kim , Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
pp. 0397
Session Fl: Memory Issues

Memory Issues (PDF)

pp. 0421

Design and Performance of a Main Memory Hardware Data Compressor (Abstract)

S. Jones , Electron. Syst. Design Group, Loughborough Univ. of Technol., UK
M. Kjelso , Electron. Syst. Design Group, Loughborough Univ. of Technol., UK
M. Gooch , Electron. Syst. Design Group, Loughborough Univ. of Technol., UK
pp. 0423

Performance Assessment of Contents Management in Multilevel On-Chip Caches (Abstract)

V. Vinals , Dept. de Inf. e Ingenieria de Sistemas, Zaragoza Univ., Spain
P. Ibanez , Dept. de Inf. e Ingenieria de Sistemas, Zaragoza Univ., Spain
pp. 0431

Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented Applications (Abstract)

K. Ghose , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
P.M. Kogge , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
K.R. Desai , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
pp. 0441
Session F2: Distributed Systems

Comparing Performances and Quality of Service of Group Communication Protocols (Abstract)

E. Pagani , Dipartimento di Inf., Milan Univ., Italy
G.P. Rossi , Dipartimento di Inf., Milan Univ., Italy
pp. 0451

Experience of Adaptive Replication in Distributed File Systems (Abstract)

A. Corradi , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
G. Cabri , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
F. Zambonelli , Dipartimento di Elettronica Inf. e Sistemistica, Bologna Univ., Italy
pp. 0459

A New Control Service Model Based on CORBA for Distributed Multimedia Objects (Abstract)

Ok-Bae Chang , Dept. of Comput. Sci. & Stat., Mokpo Nat. Univ., Chonnam, South Korea
Jae Soo Yoo , Dept. of Comput. Sci. & Stat., Mokpo Nat. Univ., Chonnam, South Korea
Han-Suk Choi , Dept. of Comput. Sci. & Stat., Mokpo Nat. Univ., Chonnam, South Korea
pp. 0467
Session F3: Formal Specification and Multimedia

Hardware/Software Co-Design of Communication Protocols (Abstract)

J. Wytrebowicz , Praktische Inf. IV, Mannheim Univ., Germany
S. Budkowski , Praktische Inf. IV, Mannheim Univ., Germany
S. Fischer , Praktische Inf. IV, Mannheim Univ., Germany
pp. 0476

Formal Specification of Communication Protocols Based on a Timed-SDL: Validation and Performance Prospects (Abstract)

Chie Dou , Dept. of Electr. Eng., Nat. Yunlin Inst. of Technol., Taiwan
pp. 0484

Formal Specification of Communication Protocols with Object-Based ECATNets (Abstract)

M. Maouche , Inst. d'Inf., Constantine Univ., Algeria
K. Barkaoui , Inst. d'Inf., Constantine Univ., Algeria
M. Bettaz , Inst. d'Inf., Constantine Univ., Algeria
pp. 0492
Session G1: Co-Processors

The Design of a Specialised Processor for the Simulation of Sintering (Abstract)

A. Postula , Dept. of Electr. & Comput. Eng., Queensland Univ., Brisbane, Qld., Australia
P. Logothetis , Dept. of Electr. & Comput. Eng., Queensland Univ., Brisbane, Qld., Australia
D. Abramson , Dept. of Electr. & Comput. Eng., Queensland Univ., Brisbane, Qld., Australia
pp. 0501

Real-Time Scheduling Co-Processor in Hardware for Single and Multiprocessor Systems (Abstract)

J. Starner , Dept. of Real-Time Comput. Syst., Malardalens Univ., Vasteras, Sweden
J. Furunas , Dept. of Real-Time Comput. Syst., Malardalens Univ., Vasteras, Sweden
J. Adomat , Dept. of Real-Time Comput. Syst., Malardalens Univ., Vasteras, Sweden
L. Lindh , Dept. of Real-Time Comput. Syst., Malardalens Univ., Vasteras, Sweden
pp. 0509
Session G2 1: Image Processing

Parallel Set Operations with Visual Data (Abstract)

P. Zemanek , Fac. of Electr. Eng., Czech Tech. Univ., Prague, Czech Republic
pp. 0529

Parallel Approaches to the Segmentation of Free-Hand Drawings (Abstract)

R.C. Canham , Dept. of Electron., York Univ., UK
S.L. Smith , Dept. of Electron., York Univ., UK
A.M. Tyrrell , Dept. of Electron., York Univ., UK
pp. 0537
Session G2 2: Parallel Software Engineering

Efficient Program Composition on Parix by the Ensemble Methodology (Abstract)

J.Y. Cotronis , Dept. of Inf., Athens Univ., Greece
pp. 0545

Paradigms for Parallel Dynamic Programming (Abstract)

J. Roda , Centro Superior de Inf., La Laguna Univ., Spain
C. Rodriguez , Centro Superior de Inf., La Laguna Univ., Spain
F. Garcia , Centro Superior de Inf., La Laguna Univ., Spain
D. Gonzalez , Centro Superior de Inf., La Laguna Univ., Spain
F. Almeida , Centro Superior de Inf., La Laguna Univ., Spain
pp. 0553
Session 63: Operating System and Network Support

The Design and Implementation of a Multimedia Storage Server to Support Video-on-Demand Applications (Abstract)

A. Garcia-Martinez , Univ. Autonoma de Madrid, Spain
A. Molano , Univ. Autonoma de Madrid, Spain
A. Vina , Univ. Autonoma de Madrid, Spain
pp. 0564

Architecture and Implementation for Scalable Transfer of Live Videos in Multimedia Applications (Abstract)

R. Hess , Dept. of Comput. Sci., Tech. Univ. Dresden, Germany
T. Hutschenreuther , Dept. of Comput. Sci., Tech. Univ. Dresden, Germany
A. Schill , Dept. of Comput. Sci., Tech. Univ. Dresden, Germany
R. Lehmann , Dept. of Comput. Sci., Tech. Univ. Dresden, Germany
pp. 0572

Automatic Scheduling of Applications with Temporal QoS Constraints: A Case Study (Abstract)

I. Demeure , Dept. Inf., CNRS, Paris, France
J. Farhat-Gissler , Dept. Inf., CNRS, Paris, France
pp. 0581
Session H 1: Novel Processor Architectures

Towards Extremely Fast Context Switching in a Block-Multithreaded Processor (Abstract)

W. Grunewald , Dept. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
T. Ungerer , Dept. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 0592

Low-Power Embedded Microprocessor Design (Abstract)

C. Arm , Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
S. Durand , Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
T. Schneider , Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
C. Piguet , Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
M. Stegers , Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
J.-M. Masgonty , Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
pp. 0600

A Fast Capability Extension to a RISC Architecture (Abstract)

P. Vasek , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
K. Ghose , Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA
pp. 0606
Session H3: Operational Considerations

Broadcast with Time and Causality Constraints for Multimedia Applications (Abstract)

M. Singhal , IRISA, Rennes, France
R. Prakash , IRISA, Rennes, France
M. Raynal , IRISA, Rennes, France
R. Baldoni , IRISA, Rennes, France
pp. 0617

Causal Modeling of a Video-on-Demand System Using Predicate/Transition Net Formalism (Abstract)

T. Pyssysalo , Digital Syst. Lab., Helsinki Univ. of Technol., Espoo, Finland
L. Ojala , Digital Syst. Lab., Helsinki Univ. of Technol., Espoo, Finland
pp. 0625

Statistical Admission Control in Video Servers with Variable Bit-Rate Streams and Constant Time Length Retrieval (Abstract)

E. Biersack , Inst. Eurecom, Sophia Antipolis, France
F. Thiesse , Inst. Eurecom, Sophia Antipolis, France
pp. 0633
Session 11: Superscalar Architectures

Instruction Scheduling for a Superscalar Architecture (Abstract)

R. Collins , Hertfordshire Univ., Hatfield, UK
G.B. Steven , Hertfordshire Univ., Hatfield, UK
pp. 0643

Load Balancing in Superscalar Architectures (Abstract)

E.S.T. Fernandes , COPPE, Univ. Federal do Rio de Janeiro, Brazil
A. Wolfe , COPPE, Univ. Federal do Rio de Janeiro, Brazil
E.M.C. Filho , COPPE, Univ. Federal do Rio de Janeiro, Brazil
pp. 0651
94 ms
(Ver 3.1 (10032016))