The Community for Technology Leaders
European Design Automation Conference with EURO-VHDL (1995)
Brighton, Great Britain
Sept. 18, 1995 to Sept. 22, 1995
ISBN: 0-8186-7156-4
TABLE OF CONTENTS

Welcome (PDF)

pp. xv
Session D-01: System Level Synthesis

Device selection for system partitioning (Abstract)

W. Rosenstiel , Comput. Sci. Res. Center, Karlsruhe Univ., Germany
O. Bringmann , Comput. Sci. Res. Center, Karlsruhe Univ., Germany
U. Weinmann , Comput. Sci. Res. Center, Karlsruhe Univ., Germany
pp. 2

A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes (Abstract)

M. Schwiegershausen , Lab. fur Informationstechnol., Hannover Univ., Germany
P. Pirsch , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 8

KANDIS-a tool for construction of mixed analog/digital systems (Abstract)

P. Oehler , Frankfurt Univ., Germany
G. Grimm , Frankfurt Univ., Germany
K. Waldschmidt , Frankfurt Univ., Germany
pp. 14
Session D-02: Information Modeling

Information model of a compound graph representation for system and architecture level design (Abstract)

P. Conradi , Center for Microelectronics, Kaiserslautern Univ., Germany
pp. 22

A core information model of VHDL (Abstract)

H.J. Kahn , Dept. of Comput. Sci., Bucharest Tech. Univ., Romania
C.A. Giumale , Dept. of Comput. Sci., Bucharest Tech. Univ., Romania
pp. 28

Practical inter-operation of CAD tools using a flexible procedural interface (Abstract)

J. Pye , Dept. of Comput. Sci., Manchester Univ., UK
M. Brown , Dept. of Comput. Sci., Manchester Univ., UK
N. Filer , Dept. of Comput. Sci., Manchester Univ., UK
J. Heaton , Dept. of Comput. Sci., Manchester Univ., UK
Z. Moosa , Dept. of Comput. Sci., Manchester Univ., UK
pp. 34
Session D-03: Timing Issues in Synthesis

Timing optimization by bit-level arithmetic transformations (Abstract)

P. Six , IMEC, Leuven, Belgium
L. Rijnders , IMEC, Leuven, Belgium
Z. Sahraoui , IMEC, Leuven, Belgium
H. De Man , IMEC, Leuven, Belgium
pp. 48

Exploiting power-up delay for sequential optimization (Abstract)

A. Aziz , Cadence Berkeley Labs., Berkeley, CA, USA
V. Singhal , Cadence Berkeley Labs., Berkeley, CA, USA
C. Pixley , Cadence Berkeley Labs., Berkeley, CA, USA
R.K. Brayton , Cadence Berkeley Labs., Berkeley, CA, USA
pp. 54

Tree restructuring approach to mapping problem in cellular-architecture FPGAs (Abstract)

N. Buddi , Synopsys Inc., Beaverton, OR, USA
N. Ramineni , Synopsys Inc., Beaverton, OR, USA
M. Chrzanowska-Jeske , Synopsys Inc., Beaverton, OR, USA
pp. 60

Generating several solutions for the scheduling problem in high-level synthesis (Abstract)

H. Achatz , Lehrstuhl Rechnerstrukturen, Passau Univ., Germany
pp. 66
Session D-04: Placement and Routing

Post routing performance optimization via tapered link insertion and wiresizing (Abstract)

T. Xue , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.S. Kuh , Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 74

Performance-oriented placement and routing for field-programmable gate arrays (Abstract)

J.L. Ganley , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.P. Cohoon , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
G. Robins , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
M.J. Alexander , Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 80

Layout synthesis for datapath designs (Abstract)

M. Chrzanowska-Jeske , Dept. of Electr. Eng., Portland State Univ., OR, USA
N. Buddi , Dept. of Electr. Eng., Portland State Univ., OR, USA
C.L. Saxe , Dept. of Electr. Eng., Portland State Univ., OR, USA
pp. 86

An investigation of iterative routing algorithms (Abstract)

D. Edwards , Dept. of Comput. Sci., Manchester Univ., UK
Z. Moosa , Dept. of Comput. Sci., Manchester Univ., UK
pp. 91
Session D-05: Different Aspects of Testability Improvements

Bottleneck removal algorithm for dynamic compaction and test cycles reduction (Abstract)

S.T. Chakradhar , NEC Res. Inst., Princeton, NJ, USA
A. Raghunathan , NEC Res. Inst., Princeton, NJ, USA
pp. 98

On generating compact test sequences for synchronous sequential circuits (Abstract)

S.M. Reddy , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz , Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 105

Partial scan selection for user-specified fault coverage (Abstract)

F. Brglez , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
C. Gloster , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 111

Testable synthesis of high complex control devices (Abstract)

F. Fummi , Dipartimento di Elettronica, Politecnico di Milano, Italy
U. Rovati , Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto , Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 117
Session D-06: Architectural Synthesis

A memory selection algorithm for high-performance pipelines (Abstract)

D.D. Gajski , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
S. Bakshi , Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 124

Area efficient DSP datapath synthesis (Abstract)

A.A. Duncan , Dept. of Eng., Aberdeen Univ., UK
D.C. Hendry , Dept. of Eng., Aberdeen Univ., UK
pp. 130

Metric-based transformations for self testable VLSI designs with high test concurrency (Abstract)

M. Vahidi , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu , Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 136
Session D-07: Partitioning and Floorplanning

On implementation choices for iterative improvement partitioning algorithms (Abstract)

L.W. Hagen , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
A.B. Kahng , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J.-H. Huang , Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 144

Multiway netlist partitioning onto FPGA-based board architectures (Abstract)

M. Glesner , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Darmstadt, Germany
U. Ober , Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Darmstadt, Germany
pp. 150
Session D-O8: Simulation and Partitioning of Hardware/Software Systems

Scalable performance scheduling for hardware-software cosynthesis (Abstract)

Th. Benner , Inst. fur Datenverarbeitungsanlagen, Braunschweig, Germany
R. Ernst , Inst. fur Datenverarbeitungsanlagen, Braunschweig, Germany
A. Osterling , Inst. fur Datenverarbeitungsanlagen, Braunschweig, Germany
pp. 164

Cosimulation of real-time control systems (Abstract)

T. Huttunen , VTT Electron., Oulu, Finland
K. Tiensyrja , VTT Electron., Oulu, Finland
J.-P. Soininen , VTT Electron., Oulu, Finland
H. Heusala , VTT Electron., Oulu, Finland
pp. 170

A hardware/software partitioning algorithm for pipelined instruction set processor (Abstract)

A. Shiomi , Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
M. Imai , Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
N.N. Binh , Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
N. Hikichi , Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
pp. 176
Session D-09: Fault Modelling and Delay Testing

A unified approach to the extraction of realistic multiple bridging and break faults (Abstract)

G. Spiegel , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
A.P. Stroele , Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 184

Quality considerations in delay fault testing (Abstract)

S. Pilarski , Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
A. Pierzynska , Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 196

Path delay ATPG for standard scan design (Abstract)

H. Wittmann , Dept. of Electr. Eng., Tech. Univ. Munchen, Germany
M. Henftling , Dept. of Electr. Eng., Tech. Univ. Munchen, Germany
pp. 202
Session D-11: Analog & Timing Modelling

Delay modelling improvement for low voltage applications (Abstract)

M. Robert , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
J.M. Daga , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
D. Auvergne , Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 216

Functional-level analog macromodeling with piecewise linear signals [analog amplifier] (Abstract)

J. Dabrowski , Inst. of Electron., Silesian Tech. Univ., Gliwice, Poland
pp. 222
Session D-12: ATPG and Speed-Up Techniques

FOGBUSTER: an efficient algorithm for sequential test generation (Abstract)

H.T. Vierhaus , German Nat. Res. Center for Comput. Sci., St. Augustin, Germany
U. Glaser , German Nat. Res. Center for Comput. Sci., St. Augustin, Germany
pp. 230

An adaptive distributed algorithm for sequential circuit test generation (Abstract)

M. Bushnell , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
P. Agrawal , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
V. Agrawal , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
J. Sienicki , Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 236

Search space reduction through clustering in test generation (Abstract)

H. De Man , IMEC, Leuven, Belgium
P. Six , IMEC, Leuven, Belgium
Z. Sahraoui , IMEC, Leuven, Belgium
I. Bolsens , IMEC, Leuven, Belgium
pp. 242

A formal non-heuristic ATPG approach (Abstract)

M. Henftling , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
H. Wittmann , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
K.J. Antreich , Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 248
Session D-13: Simulation and Debugging of System Descriptions

Debugging of behavioral VHDL specifications by source level emulation (Abstract)

G. Koch , Forschungszentrum Inf., Karlsruhe Univ., Germany
U. Kebschull , Forschungszentrum Inf., Karlsruhe Univ., Germany
W. Rosenstiel , Forschungszentrum Inf., Karlsruhe Univ., Germany
pp. 256

A backplane approach for cosimulation in high-level system specification environments (Abstract)

S. Schmerler , Forschungszentrum Inf., Karlsruhe Univ., Germany
K.D. Muller-Glaser , Forschungszentrum Inf., Karlsruhe Univ., Germany
Y. Tanurhan , Forschungszentrum Inf., Karlsruhe Univ., Germany
pp. 262

Integration of VHDL into a system design environment (Abstract)

M. Luck , Dortmund Univ., Germany
H. Schroder , Dortmund Univ., Germany
L. Schwoerer , Dortmund Univ., Germany
pp. 268

An improved relaxation approach for mixed system analysis with several simulation tools (Abstract)

V.B. Dmitriev-Zdorov , Taganrog Radioeng. Univ., Taganrog, Russia
B. Klaassen , Taganrog Radioeng. Univ., Taganrog, Russia
pp. 274
Session D-14: Logic Synthesis and Optimization

Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs) (Abstract)

N. Kanopoulos , Comput. Technol. Inst., Patras Univ., Greece
T. Karoubalis , Comput. Technol. Inst., Patras Univ., Greece
G.Ph. Alexiou , Comput. Technol. Inst., Patras Univ., Greece
pp. 282

Computing subsets of equivalence classes for large FSMs (Abstract)

P. Camurati , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
S. Quer , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
G. Cabodi , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 288

Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions (Abstract)

M. Poncino , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
E. Macii , Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 294

ODE: output direct state machine encoding (Abstract)

J. Forrest , Dept. of Comput., Univ. of Manchester Inst. of Sci. & Technol., UK
pp. 600
Session D-15: Framework Architectures

Model of conceptual design of complex electronic systems (Abstract)

A.L. Stempkovsky , World Lab., Moscow, Russia
A.N. Soloviev , World Lab., Moscow, Russia
pp. 302

Cooperative concurrency control for design environments (Abstract)

A. Bredenfeld , Gesellschaft fur Math. und Datenverarbeitung mbH, St. Augustin, Germany
pp. 308

Reduced design time by load distribution with CAD framework methodology information (Abstract)

A. Kunzmann , Comput. Sci. Res. Centre, Karlsruhe Univ., Germany
J. Schubert , Comput. Sci. Res. Centre, Karlsruhe Univ., Germany
W. Rosenstiel , Comput. Sci. Res. Centre, Karlsruhe Univ., Germany
pp. 314
Session D-16: Hardware/Software System Design

System modeling, hardware-software codesign, and mixed modeling with hardware description languages (Abstract)

S. Mohanty , AT&T Bell Labs., Allentown, PA, USA
P.A. Wilsey , AT&T Bell Labs., Allentown, PA, USA
pp. 322

Closeness metrics for system-level functional partitioning (Abstract)

D.D. Gajski , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
F. Vahid , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 328

Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems (Abstract)

S. Srinivasan , Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha , Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 334

Performance-complexity analysis in hardware-software codesign for real-time systems (Abstract)

V.V. Toporkov , Dept. of Comput. Eng., Moscow Power Eng. Inst., Russia
pp. 340
Session D-17: EMC and Thermal Effects

Prediction of radiated electromagnetic emissions from PCB traces based on Green dyadics (Abstract)

G. Vecchi , High Design Technol., Torino, Italy
E. Leroux , High Design Technol., Torino, Italy
F. Canavero , High Design Technol., Torino, Italy
pp. 354

Software system for semiconductor devices, monolith and hybrid IC's thermal analysis (Abstract)

I.A. Kharitonov , Moscow Univ. of Electron. & Math., Russia
N.I. Rybov , Moscow Univ. of Electron. & Math., Russia
K.O. Petrosjanc , Moscow Univ. of Electron. & Math., Russia
P.P. Maltcev , Moscow Univ. of Electron. & Math., Russia
pp. 360
Session D-18: New Ideas in Synthesis

An approach to guided incremental specification (Abstract)

S. Marz-Rossel , Corp. Res. & Dev., Siemens AG, Munich, Germany
T. Gabler , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 368

Semi-dynamic scheduling of synchronization-mechanisms (Abstract)

W. Ecker , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 374

A design system for special purpose processors based on architectures for distributed processing (Abstract)

K. Shirai , Sch. of Sci. & Eng., Waseda Univ., Tokyo, Japan
J. Hiwatashi , Sch. of Sci. & Eng., Waseda Univ., Tokyo, Japan
pp. 380

Formulation and evaluation of scheduling techniques for control flow graphs (Abstract)

M. Rahmouni , Lab. TIMA/INPG, Grenoble, France
A.A. Jerraya , Lab. TIMA/INPG, Grenoble, France
pp. 386
Session V-01 : Simulation

A high performance VHDL simulator for large systems design (Abstract)

S. Hodgson , Design Autom. Centre, ICL, Manchester, UK
A. Smith , Design Autom. Centre, ICL, Manchester, UK
Z. Shaar , Design Autom. Centre, ICL, Manchester, UK
pp. 394

Use of embedded scheduling to compile VHDL for effective parallel simulation (Abstract)

J. Willis , Div. of Syst. Technol. & Archit., IBM Corp., Rochester, MN, USA
Zhiyuan Li , Div. of Syst. Technol. & Archit., IBM Corp., Rochester, MN, USA
Tsang-Puu Lin , Div. of Syst. Technol. & Archit., IBM Corp., Rochester, MN, USA
pp. 400

Latest benchmark results of VHDL simulation systems (Abstract)

E. Rohm , Semicond. Div., Siemens AG, Munich, Germany
pp. 406
Session V-02: Formal Methods

Towards verifying VHDL descriptions of processors (Abstract)

L. Arditi , CNRS, Nice Univ., Sophia Antipolis, France
H. Collavizza , CNRS, Nice Univ., Sophia Antipolis, France
pp. 414

A native process algebra for VHDL (Abstract)

P.T. Breuer , ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
N.M. Madrid , ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
pp. 420
Session V-03: Language Development

Inheritance concept for signals in object-oriented extensions to VHDL (Abstract)

G. Schumacher , Dept. of Comput. Sci., Carl von Ossietzky Univ., Oldenburg, Germany
W. Nebel , Dept. of Comput. Sci., Carl von Ossietzky Univ., Oldenburg, Germany
pp. 428

Object-oriented high-level modeling of system components for the generation of VHDL code (Abstract)

S. Schulze , Dept. of Comput. Sci., Tech. Univ. Chemnitz, Germany
D. Monjau , Dept. of Comput. Sci., Tech. Univ. Chemnitz, Germany
K. Agsteiner , Dept. of Comput. Sci., Tech. Univ. Chemnitz, Germany
pp. 436
Session V-04: Behavioral Synthesis from VHDL

High-level synthesis and codesign methods: An application to a Videophone Codec (Abstract)

P. Paulin , SGS-Thomson Microelectron., Crolles, France
J. Frehel , SGS-Thomson Microelectron., Crolles, France
J.-C. Herluison , SGS-Thomson Microelectron., Crolles, France
M. Harrand , SGS-Thomson Microelectron., Crolles, France
E. Berrebi , SGS-Thomson Microelectron., Crolles, France
F. Nacabul , SGS-Thomson Microelectron., Crolles, France
C. Liem , SGS-Thomson Microelectron., Crolles, France
pp. 444

Timing constraint specification and synthesis in behavioral VHDL (Abstract)

A. Doboli , Dept. of Comput. Sci. & Eng., Tech. Univ. of Timisoara, Romania
P. Eles , Dept. of Comput. Sci. & Eng., Tech. Univ. of Timisoara, Romania
Z. Peng , Dept. of Comput. Sci. & Eng., Tech. Univ. of Timisoara, Romania
K. Kuchcinski , Dept. of Comput. Sci. & Eng., Tech. Univ. of Timisoara, Romania
pp. 452

VHDL-based communication- and synchronization synthesis (Abstract)

M. Huber , Corp. Res. & Dev., Siemens AG, Munich, Germany
W. Ecker , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 458
Session V-05: Design Techniques

A reuse scenario for the VHDL-based hardware design flow (Abstract)

S. Marz-Rossel , Corp. Res. & Dev., Siemens AG, Munich, Germany
M. Schutz , Corp. Res. & Dev., Siemens AG, Munich, Germany
R. Henftling , Corp. Res. & Dev., Siemens AG, Munich, Germany
V. Preis , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 464

VHDL based design methodology for hierarchy and component re-use (Abstract)

Hong Ding , TIMA Lab., Grenoble, France
P. Kission , TIMA Lab., Grenoble, France
A.A. Jerraya , TIMA Lab., Grenoble, France
pp. 470

Quantifying design productivity: an effort distribution analysis (Abstract)

H. Kobayashi , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
M. Joshi , Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 476

VHDL quality: synthesizability, complexity and efficiency evaluation (Abstract)

M. Sturlesi , Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
M. Mastretti , Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
R. Sarvello , Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
S. Tomasello , Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
M.L. Busi , Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
pp. 482
Session V-07: System Level Design

Design and use of a system-level specification and verification methodology (Abstract)

A.C. Bruce , Design Autom. Centre, ICL, Manchester, UK
M.M.K. Hashmi , Design Autom. Centre, ICL, Manchester, UK
pp. 490

Design management requirements for hardware description languages (Abstract)

F.R. Wagner , Inst. de Inf., Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 496

An effective system development environment based on VHDL prototyping (Abstract)

L. Berrojo , Dept. of Design Technol., TGI S.A., Madrid, Spain
L. Entrena , Dept. of Design Technol., TGI S.A., Madrid, Spain
S. Olcoz , Dept. of Design Technol., TGI S.A., Madrid, Spain
pp. 502

Procedure exlining: a new system-level specification transformation (Abstract)

F. Vahid , Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 508
Session V-08: Modeling

LibQA - library quality assurance for VHDL synthesis and simulation (Abstract)

R.B. Stewart , SGS Thomson Microelectronics, USA
J. Phillips , SGS Thomson Microelectronics, USA
pp. 516

Generating VHDL-A-like models using ABSynth (Abstract)

F. Pellandini , Inst. of Microtechnology, Neuchatel Univ., Switzerland
V. Moser , Inst. of Microtechnology, Neuchatel Univ., Switzerland
P. Nussbaum , Inst. of Microtechnology, Neuchatel Univ., Switzerland
H.P. Amann , Inst. of Microtechnology, Neuchatel Univ., Switzerland
pp. 522

VHDL package for description of fuzzy logic controllers (Abstract)

S. Sanchez-Solano , Dept. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectronica, Sevilla, Spain
A. Barriga , Dept. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectronica, Sevilla, Spain
C.J. Jimenez , Dept. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectronica, Sevilla, Spain
D. Galan , Dept. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectronica, Sevilla, Spain
pp. 528
Session V-09: Verification and Validation

A classification of design steps and their verification (Abstract)

W. Ecker , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 536

Verification of a production cell using an automatic verification environment for VHDL (Abstract)

T. Reielts , Corp. Res. & Dev., Siemens AG, Munich, Germany
R. Herrmann , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 542

Verification of a production cell controller using symbolic timing diagrams (Abstract)

R. Schlor , OFFIS, Oldenburg, Germany
F. Korf , OFFIS, Oldenburg, Germany
pp. 548

How to efficiently build VHDL testbenches (Abstract)

M. Schutz , Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 554
User Plenary Session

A DSP ASIC design flow based on VHDL and ASIC-emulation (Abstract)

J. Andersson , Ericsson Microwave Syst. AB, Molndal, Sweden
pp. 562

System level design, a VHDL based approach (Abstract)

J. Van den Hurk , Philips Semicond., Product Concept & Application Lab. Eindhoven, Netherlands
E. Dilling , Philips Semicond., Product Concept & Application Lab. Eindhoven, Netherlands
pp. 568

A uniform design methodology for application specific digital integrated circuits in automotive applications (Abstract)

B. Mossner , Automotive Equipment Div., Robert Bosch GmbH, Reutlingen, Germany
J. Papanuskas , Automotive Equipment Div., Robert Bosch GmbH, Reutlingen, Germany
J. Hanisch , Automotive Equipment Div., Robert Bosch GmbH, Reutlingen, Germany
T. Lindenkreuz , Automotive Equipment Div., Robert Bosch GmbH, Reutlingen, Germany
pp. 574

The VHDL based design of the MIDA MPEG1 audio decoder (Abstract)

M. Paolini , CSELT, Torino, Italy
A. Finotello , CSELT, Torino, Italy
pp. 579

Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics (Abstract)

P. Chambert , Avionics & Syst. Div., Aerospatiale, Toulouse, France
P. de Chazelles , Avionics & Syst. Div., Aerospatiale, Toulouse, France
A. Jeffroy , Avionics & Syst. Div., Aerospatiale, Toulouse, France
A.A. Jerraya , Avionics & Syst. Div., Aerospatiale, Toulouse, France
M. Romdhani , Avionics & Syst. Div., Aerospatiale, Toulouse, France
pp. 585

Issues in low-power design for telecom (Abstract)

P. Vanoostende , Adv. CAD for VLSI, Alcatel-Bell, Antwerpen, Belgium
G. Van Wauwe , Adv. CAD for VLSI, Alcatel-Bell, Antwerpen, Belgium
pp. 591

Creating hierarchy in HDL-based high density FGPA design (Abstract)

C.A. Fields , Xilinx Inc., San Jose, CA, USA
pp. 594

Index of Authors (PDF)

pp. 607
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