The Community for Technology Leaders
European Design Automation Conference with EURO-VHDL (1996)
Geneva, Switzerland
Sept. 16, 1996 to Sept. 20, 1996
ISBN: 0-8186-7573-X
TABLE OF CONTENTS
Session D-01 Analog and Mixed Mode Simulation

Generalized coupling as a way to improve the convergence in relaxation-based solvers (Abstract)

Vladimir B. Dmitriev-Zdorov , Theoretical Basis of Radioengineering Department of Taganrog State Radioengineering University
pp. 0015
Session D-02 Low Power Synthesis
Session D-03 Design Experience

Implementing Fuzzy Control Systems Using VHDL and Statecharts (Abstract)

Valentina Salapura , salapura@vlsivie.tuwien.ac.at
Volker Hamann , salapura@vlsivie.tuwien.ac.at
pp. 0053
Session D-04 Timing Modeling

New Approach in Gate-Level Glitch Modelling (Abstract)

Dirk Rabe , Carl von Ossietzky University Oldenburg
pp. 0066

A New Concept for Accurate Modeling of VLSI Interconnetions and its Application for Timing Simulation (Abstract)

Bernhard Wunder , Institut fuer Technik der Informationsverarbeitung
Gunther Lehmann , Institut fuer Technik der Informationsverarbeitung
Klaus D. Mueller-Glaser , Institut fuer Technik der Informationsverarbeitung
pp. 0072
Session D-05 Design Flow and Design Management
Session D-07 Partitioning

Synthesis From Mixed Specifications (Abstract)

Vincent J. Mooney, III , Stanford University
Toshiyuki Sakamoto , Giovanni De Micheli
pp. 0114
Session D-08 Logic & FSM Synthesis

Automatic Structuring and Optimization of Hierarchical Designs (Abstract)

Heinz-Josef Eikerling , {eikerlin,rosenstiel}@peanuts.informatik.uni-tuebingen.de
Wolfgang Rosenstiel , {eikerlin,rosenstiel}@peanuts.informatik.uni-tuebingen.de
pp. 0134

Controller Optimization for Protocol Intensive Applications (Abstract)

Andrew Crews , University of California, Santa Barbara, USA crews@corona.ece.ucsb.edu, forrest@ece.ucsb.edu
Forrest Brewer , University of California, Santa Barbara, USA crews@corona.ece.ucsb.edu, forrest@ece.ucsb.edu
pp. 0140
Session D-09 BDD Optimization Techniques

Decomposed Symbolic Forward Traversals of Large Finite State Machines (Abstract)

Gianpiero Cabodi , Politecnico di Torino
Stefano Quer , Politecnico di Torino
Paolo Camurati , Politecnico di Torino
pp. 0170
Session D-10 Codesign Methodology and Cospecification
Session D-11 System Level Design & Synthesis

Instruction Selection for Embedded DSPs with Complex Instructions (Abstract)

Rainer Leupers , University of Dortmund
Peter Marwedel , University of Dortmund
pp. 0200

Hierarchical Behavioural Partitioning for Multicomponent Synthesis (Abstract)

Nand Kumar , Triquest Design Automation
Vinoo Srinivasan , Laboratory for Digital Design Environments, ECECS University of Cincinnati, Cincinnati, OH 45221-0030
Ranga Vemuri , Laboratory for Digital Design Environments, ECECS University of Cincinnati, Cincinnati, OH 45221-0030
pp. 0212
Session D-12 New Aspects on Testing

Testable Path Delay Fault Cover for Sequential Circuits (Abstract)

Angela Krstic , University of California, Santa Barbara, CA
Srimat T. Chakradhar , C&C Research Laboratories, NEC USA,
Kwang-Ting Cheng , University of California, Santa Barbara, CA
pp. 0220

Efficient Random Testing with Global Weights (Abstract)

Arno Kunzmann , Forschungszentrum Informatik (FZI) Email kunzmann@fzi.de
pp. 0227
Session D-13 Codesign Methodology & Cosimulation

An Integrated Approach to Engineering Computer Systems (Abstract)

D.Gareth Evans , Institute of Science and Technology - University of Manchester, UK
Peter N. Green , Institute of Science and Technology - University of Manchester, UK
Derrick Morris , Institute of Science and Technology - University of Manchester, UK
pp. 0264
Session D-15 Key Technologies and CAD of Microsystems
Session D-16 Asynchronous Synthesis and Storage Optimization

Automatic Synthesis of Extended Burst-Mode Circuits Using Generalized C-elements (Abstract)

Kenneth Y. Yun , University of California, San Diego kyy@UCSD.EDU
pp. 0290

Storage Optimization by Replacing Some Flip-Flops with Latches (Abstract)

Tsung-Yi Wu , Tsing Hua University, Hsin-Chu, Taiwan 30043
Youn-Long Lin , Tsing Hua University, Hsin-Chu, Taiwan 30043
pp. 0296

Assignment of Storage Values to Sequential Read-Write Memories (Abstract)

Sabih H. Gerez , Univeristy of Twente
Erwin G. Woutersen , Univeristy of Twente
pp. 0302
Session D-17 Modelling, Simulation of Microsystems and Multi Layer Routing in PCBs

Simulation and Design Optimization of Microsystems Based on Standard Simulators and Adaptive Search Techniques (Abstract)

S. Meinzer , Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
A. Quinte , Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
M. Gorges-Schleuter , Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
W. Jakob , Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
W. Suess , Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
H. Eggert , Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
pp. 0322
Session D-18 Timing Issues in Synthesis

Clock Optimization for High-Performance Pipelined Design (Abstract)

Hsiao-ping Juan , University of California, Irvine
Daniel D. Gajski , University of California, Irvine
Smita Bakshi , University of California, Irvine
pp. 0330
Session D-19 Physical Design for Deep Submicron
Session D-20 Architectural Synthesis Techniques

Component Selection in Resource Shared and Pipelined DSP Applications (Abstract)

Smita Bakshi , University of California, Irvine
Daniel D. Gajski , University of California, Irvine
Hsiao-Ping Juan , University of California, Irvine
pp. 0370

Module Assignment for Low Power (Abstract)

Jui-Ming Chang , juiming@danube.usc.edu massoud@danube.usc.edu
Massoud Pedram , juiming@danube.usc.edu massoud@danube.usc.edu
pp. 0376

A High-Level Synthesis Approach to Optimum Design of Self-Checking Circuits (Abstract)

Anna Antola , Dipartimento di Elettronica e Informazione, Politecnico di Milano
Vincenzo Piuri , Dipartimento di Elettronica e Informazione, Politecnico di Milano
Mariagiovanna Sami , Dipartimento di Elettronica e Informazione, Politecnico di Milano
pp. 0382
Session D-22 CAD for Analog Circuit

Global Stacking for Analog Circuits (Abstract)

Bogdan G. Arsintescu , Delft University of Technology
Sorin A. Spanoche , University of Bucharest
pp. 0392
Session V-01 Analysis Tools
Session V-02 Beyond VHDL
Session V-04 Fault Modeling and Design for Testability

Model generation of test logic for macrocell based designs (Abstract)

E. de la Torre , Univ. Politecnica de Madrid, Spain
J. Calvo , Univ. Politecnica de Madrid, Spain
J. Uceda , Univ. Politecnica de Madrid, Spain
pp. 0456

A Fault Model for VHDL Descriptions at the Register Transfer Level (Abstract)

T. Riesgo , Universidad PolitTcnica de Madrid
J. Uceda , Universidad PolitTcnica de Madrid
pp. 0462

The Maximal VHDL Subset with a Cycle-Level Abstraction (Abstract)

Wendell C. Baker , {wbaker,newton}@eecs.berkeley.edu Department of Electrical Engineering and Computer Science University of California, Berkeley, 94720, USA
A. Richard Newton , {wbaker,newton}@eecs.berkeley.edu Department of Electrical Engineering and Computer Science University of California, Berkeley, 94720, USA
pp. 0470

A Refinement Calculus for VHDL (Abstract)

Peter T. Breuer , Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
Carlos Delgado Kloos , Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
Natividad Martinez Madrid , Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
Andres Marin , Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
Luis Sanchez , Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
pp. 0482
Session V-06 Modeling Methodologies

Analysis of Different Protocol Description Styles in VHDL for High-Level Synthesis (Abstract)

Maher Rahmouni , Coppe/UFRJ - Program of Electric Engineering
Polen Kission , Coppe/UFRJ - Program of Electric Engineering
Ahmed A. Jerraya , Coppe/UFRJ - Program of Electric Engineering
Luci Pirmez , Coppe/UFRJ - Program of Electric Engineering
A. Pedroza , Coppe/UFRJ - Program of Electric Engineering
A. Mesquita , Coppe/UFRJ - Program of Electric Engineering
pp. 0490

Hardware Synthesis from Requirement Specifications (Abstract)

Konrad Feyerabend , Oldenburg University
Rainer Schloer , OFFIS, Escherweg 2, D-26121 Oldenburg, Rainer.Schloer@OFFIS.Uni-Oldenburg.DE
pp. 0496

Stepwise Refinement of Behavioral VHDL Specifications by Separation of Synchronization and Functionality (Abstract)

Claus Schneider , Siemens AG, Corporate Research and Development
Wolfgang Ecker , Siemens AG, Corporate Research and Development
pp. 0509
Session V-07 Synthesis

Specification and Management of Timing Constraints in Behavioral VHDL (Abstract)

Francesco Curatelli , DIBE - University of Genoa
Leonardo Mangeruca , DIBE - University of Genoa
Marco Chirico , DIBE - University of Genoa
pp. 0522
Session V-08 System Level Design

An extendible MIPS-I processor kernel in VHDL for hardware/software co-design (Abstract)

Michael Gschwind , Technische UniversitSt Wien
Dietmar Maurer , Technische UniversitSt Wien
pp. 0548
Session V-09 VHDL & Mixed Signal Design

VHDL 1076.1 - Analog and Mixed-Signal Extensions to VHDL (Abstract)

Ernst Christen , Analogy Inc.
Kenneth Bakalar , Compass Design Automation
pp. 0556
Author Index

Index of Authors (PDF)

pp. 0577
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