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European Test Workshop, IEEE (2003)
Maastricht, The Netherlands
May 25, 2003 to May 28, 2003
ISSN: 1530-1877
ISBN: 0-7695-1908-3

Foreword (PDF)

pp. ix

Committees (PDF)

pp. x

TPI for Improving PR Fault Coverage of Boolean and Three-State Circuits (Abstract)

A. J. van de Goor , Delft University of Technology
M. J. Geuzebroek , Delft University of Technology
pp. 3

On the Selection of Efficient Arithmetic Additive Test Pattern Generators (Abstract)

E. Lupon , Universitat Polit?cnica de Catalunya
L. Balado , Universitat Polit?cnica de Catalunya
L. Garcia , Universitat Polit?cnica de Catalunya
S. Manich , Universitat Polit?cnica de Catalunya
J. Rius , Universitat Polit?cnica de Catalunya
R. Rodriguez , Universitat Polit?cnica de Catalunya
J. Figueras , Universitat Polit?cnica de Catalunya
pp. 9

Parity-Based Output Compaction for Core-Based SOCs (Abstract)

Alex Orailoglu , University of California at San Diego
Ozgur Sinanoglu , University of California at San Diego
pp. 15
Memory Test

Defect-Oriented Dynamic Fault Models for Embedded-SRAMs (Abstract)

Simone Borri , Infineon Technologies France
Patrick Girard , Laboratoire d?Informatique, Robotique et Micro?lectronique
Serge Pravossoudovitch , Laboratoire d?Informatique, Robotique et Micro?lectronique
Magali Hage-Hassan , Infineon Technologies France and Institut des Sciences de l?Ing?nieur de Montpellier
Arnaud Virazel , Laboratoire d?Informatique, Robotique et Micro?lectronique
pp. 23

Importance of Dynamic Faults for New SRAM Technologies (Abstract)

John Delos Reyes , Intel Corporation
Said Hamdioui , Delft University of Technology and Intel Corporation
Ad J. van de Goor , Delft University of Technology
Rob Wadsworth , STMicroelectronics
pp. 29

Yield Analysis for Repairable Embedded Memories (Abstract)

Harald Vranken , Philips Research
Erik Jan Marinissen , Philips Research
Krishnendu Chakrabarty , Duke University
Aishwarya Dubey , Indian Institute of Technology
Clemens Wouters , Philips Semiconductors
Anuja Sehgal , Duke University
pp. 35
Asynchronous Test

Scan Test Strategy for Asynchronous-Synchronous Interfaces (Abstract)

Octavian Petre , MESA+ Research Institute
Hans G. Kerkhoff , MESA+ Research Institute
pp. 43
SoC Testing

An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling (Abstract)

Erik Larsson , Link?ping University
Julien Pouget , Link?ping University
Zebo Peng , Link?ping University
Marie-Lise Flottes , Montpellier 2 University
Bruno Rouzeyre , Montpellier 2 University
pp. 51

Control-Aware Test Architecture Design for Modular SOC Testing (Abstract)

Sandeep Kumar Goel , Philips Research Laboratories
Erik Jan Marinissen , Philips Research Laboratories
pp. 57
Issues in Test Application

Automating the Device Interface Board Modeling for Virtual Test (Abstract)

Fritz Raczkowski , FH Joanneum Kapfenberg
Gunter Krampl , Infineon Technologies AG
Marco Rona , Infineon Technologies AG
pp. 71
Defect-Oriented Test

Signal Integrity Loss in Bus Lines due to Open Shielding Defects (Abstract)

Joan Figueras , Universitat Politècnica de Catalunya
pp. 79

Process-Variability Aware Delay Fault Testing of ΔV<sub>T</sub> and Weak-Open Defects (Abstract)

Jos? Pineda de Gyvez , Philips Research Laboratories
Guido Gronthoud , Philips Research Laboratories
Daniel Arum?-Delgado , Polytechnical University of Catalunya
Rosa Rodr?guez-Monta? , Polytechnical University of Catalunya
pp. 85

Modeling Feedback Bridging Faults With Non-Zero Resistance (Abstract)

Bernd Becker , Albert-Ludwigs-University
Michel Renovell , LIRMM - UMII
Ilia Polian , Albert-Ludwigs-University
Piet Engelke , Albert-Ludwigs-University
pp. 91
Functional Validation

Code Generation for Functional Validation of Pipelined Microprocessors (Abstract)

M. Sonza Reorda , Politecnico di Torino
F. Corno , Politecnico di Torino
G. Squillero , Politecnico di Torino
pp. 113
Scan and Core Testing

Enhanced P1500 Compliant Wrapper Suitable for Delay Fault Testing of Embedded Cores (Abstract)

H. G. Kerkhoff , University of Twente
H. J. Vermaak , University of Twente and Technikon Free State
pp. 121
RF, EME, and Probing
Delay Testing

On Path Selection for Delay Fault Testing Considering Operating Conditions (Abstract)

S.M. Reddy , University of Iowa
S. Kundu , Intel Corporation
B. Seshadri , Purdue University
I. Pomeranz , Purdue University
pp. 141

Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs (Abstract)

M. Renovell , Universit? Montpellier II
S. Pravossoudovitch , Universit? Montpellier II
O. H?ron , Universit? Montpellier II
P. Girard , Universit? Montpellier II
pp. 147
Exploiting 1149.1 for Debug and Core Test
Author Index

Author Index (PDF)

pp. 161
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