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European Test Workshop, IEEE (2002)
Corfu, Greece
May 26, 2002 to May 29, 2002
ISSN: 1530-1877
ISBN: 0-7695-1715-3

Foreword (PDF)

pp. viii

Committees (PDF)

pp. ix

TTTC Information (PDF)

pp. 128
Keynote Address
SoC Test
Defect Based Testing

Modeling Gate Oxide Short Defects in CMOS Minimum Transistors (Abstract)

M. Renovell , Universit? de Montpellier II
F. Azaïs , Universit? de Montpellier II
J. M. Gallière , Universit? de Montpellier II
Y. Bertrand , Universit? de Montpellier II
pp. 15

ATPG for Timing-Induced Functional Errors on Trigger Events in Hardware-Software Systems (Abstract)

Fei Xin , University of Massachusetts at Amherst
Jinzheng Peng , University of Massachusetts at Amherst
Ian G. Harris , University of Massachusetts at Amherst
Srikanth Arekapudi , University of Massachusetts at Amherst
pp. 23

Dependable Testing of Compactor MISR:A Imperceptible Problem? (Abstract)

Andrzej Hlawiczka , Silesian University of Technology
Michal Kopec , Silesian University of Technology
pp. 31

RESPIN++ - Deterministic Embedded Test (Abstract)

Hans-Joachim Wunderlich , University of Stuttgart
Rainer Dorsch , University of Stuttgart
Lars Schäfer , University of Stuttgart
pp. 37
Delay Testing

Novel ATPG Algorithms for Transition Faults (PDF)

Michael S. Hsiao , Virginia Tech
Sreejit Chakravarty , Intel Corporation
Xiao Liu , Virginia Tech
Paul J Thadikaran , Intel Corporation
pp. 47

On Selecting Testable Paths in Scan Designs (Abstract)

Seiji Kajihara , Kyushu Institute of Technology
Yun Shao , University of Iowa
Sudhakar M. Reddy , University of Iowa
Irith Pomeranz , Purdue University
pp. 53
System Test and Debug

Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips (Abstract)

Sandeep Kumar Goel , Philips Research Laboratories
Bart Vermeulen , Philips Research Laboratories
pp. 61

System Level Testing of Virtual Switch (Re-) Configuration over IP (Abstract)

Tiziana Margaria , METAFrame Technologies GmbH
Bernhard Steffen , University of Dortmund
Oliver Niese , University of Dortmund
Andrei Erochok , Siemens AG
pp. 67
Industrial Experiences: Bridging Faults and Current Test

Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting (Abstract)

Hartmut Delong , Micronas GmbH
Bernd Becker , Albert-Ludwigs-University
Jonathan Bradford , Micronas GmbH
Ilia Polian , Albert-Ludwigs-University
pp. 75
Testing Data Converters and PLLs

A High Accuracy Triangle-Wave Signal Generator for On-Chip ADC Testing (Abstract)

S. Bernard , University of Montpellier
Y. Bertrand , University of Montpellier
M. Renovell , University of Montpellier
F. Azaïs , University of Montpellier
pp. 89
Industrial Experiences: DFT and BIST

Combining Deterministic Logic BIST with Test Point Insertion (Abstract)

Harald Vranken , Philips Research Laboratories
Hans-Joachim Wunderlich , University of Stuttgart
Florian Meister , University of Stuttgart
pp. 105
Power Conscious Testing

Dynamic Test Data Transformations for Average and Peak Power Reductions (Abstract)

Ozgur Sinanoglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
Ismet Bayraktaroglu , University of California at San Diego
pp. 113

Power Constrained Preemptive TAM Scheduling (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology
Erik Larsson , Nara Institute of Science and Technology
pp. 119
Author Index

Author Index (PDF)

pp. 127
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