The Community for Technology Leaders
European Test Workshop, IEEE (2001)
Stockholm, Sweden
May 29, 2001 to June 1, 2001
ISSN: 1530-1877
ISBN: 0-7695-1016-7
TABLE OF CONTENTS

Foreword (PDF)

pp. viii

Committees (PDF)

pp. ix
Defect-Oriented Testing

Analyzing Bridging Faults Impact on EEPROM Cell Array (Abstract)

A. Pérez , ICF/L2MP-UMR CNRS 6137
J.M. Portal , ICF/L2MP-UMR CNRS 6137
pp. 3

Internal Feedback Bridging Faults in Combinational CMOS Circuits: Analysis and Testing (Abstract)

Yukiya Miura , Tokyo Metropolitan University
Shuichi Seno , Tokyo Metropolitan University
pp. 9
System-Level DFT

System-level DfT for Consumer Products (Abstract)

Frans G.M. de Jong , Philips Research
D.C.L. (Erik) van Geest , Philips Research
pp. 19
Delay Testing

A Fault Model for Function and Delay Testing (Abstract)

Joonhwan Yi , The University of Michigan, Ann Arbor
John P. Hayes , The University of Michigan, Ann Arbor
pp. 27

Demodulation Based Testing of Off-Chip Driver Performance (Abstract)

Wilfried Daehn , Hochschule Magdeburg-Stendahl
pp. 42
Case Studies

Automated Regression Testing of CTI-Systems (Abstract)

Tiziana Margaria , METAFrame Technologies GmbH
Georg Brune , Siemens AG
Andreas Hagerer , METAFrame Technologies GmbH
Bernhard Steffen , Univ. of Dortmund
Hans-Dieter Ide , Siemens AG
Oliver Niese , METAFrame Technologies GmbH
Werner Goerigk , Siemens AG
pp. 51
Analog & Mixed-Signal Testing

On-Chip Signal Level Evaluation for Mixed-Signal ICs using Digital Window Comparators (Abstract)

B. Ricco , Universit? di Bologna
D. de Venuto , Politecnico di Bari
M.J. Ohletz , Alcatel Microelectronics
pp. 68

The Use of Equivalent Fault Analysis To Improve Static D.C. Fault Diagnosis - A Potentiometric DAC Case Study (Abstract)

Y.S. Lee , The Hong Kong Polytechnic University
Mike W.T. Wong , The Hong Kong Polytechnic University
Matthew Worsman , The Hong Kong Polytechnic University
pp. 73
Transportation of Test Data

A Packet Switching Communication-Based Test Access Mechanism for System Chips (Abstract)

Mohsen Nahvi , University of British Columbia
André Ivanov , University of British Columbia
pp. 81
System-Level Testing

System Level Diagnosis-A Comparison of Two Alternative Approaches (Abstract)

Franc Novak , Jozef Stefan Institute
Maisaa Khalil , LCIS-INPG
Chantal Robach , LCIS-INPG
Alenka Zuzek , Jozef Stefan Institute
pp. 89
RTL Validation, DFT, & TPG

An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures (Abstract)

H.G. Kerkhoff , University of Twente
R.J.W.T. Tangelder , University of Twente
V.A. Zivkovic , University of Twente
pp. 106
BIST & Test Resource Partitioning

On Hardware Generation of Random Single Input Change Test Sequences (Abstract)

P. Girard , LIRMM -CNRS/Universit? Montpellier II
A. Virazel , LIRMM -CNRS/Universit? Montpellier II
R. David , Laboratoire d'Automatique de Grenoble
S. Pravossoudovitch , LIRMM -CNRS/Universit? Montpellier II
C. Landrault , LIRMM -CNRS/Universit? Montpellier II
pp. 117

Reusing Scan Chains for Test Pattern Decompression (Abstract)

Rainer Dorsch , University of Stuttgart
Hans-Joachim Wunderlich , University of Stuttgart
pp. 124
Mixed-Signal Testing

A VHDL-based Virtual Test Concept for Pre-silicon Test-program Debug (Abstract)

Marco Rona , Infineon Technologies
Gunter Krampl , Infineon Technologies
pp. 135

Using At-Speed BIST to Test LVDS Serializer/Deserializer Function (Abstract)

Magnus Eckersand , National Semiconductor/Sweden
Ken Filliter , National Semiconductor/Sweden
Fredrik Franzon , Ericsson Radio Systems/Sweden
pp. 140

Author Index (PDF)

pp. 147
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