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European Test Workshop, IEEE (2000)
Cascais, Portugal
May 23, 2000 to May 26, 2000
ISSN: 1530-1877
ISBN: 0-7695-0701-8
TABLE OF CONTENTS
Session 1A Delay Testing and Test Scheduling

Bridging the Testing Speed Gap: Design for Delay Testability (Abstract)

M. Shashaani , University of Waterloo
M. Sachdev , University of Waterloo
H. G. Kerkhoff , University of Twente
H. Speek , University of Twente
pp. 3

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences (Abstract)

S. Pravossoudovitch , Universit? Montpellier II
P. Girard , Universit? Montpellier II
R. David , INPG - CNRS - UJF
A. Virazel , Universit? Montpellier II
C. Landrault , Universit? Montpellier II
pp. 9
Session 1B Scan and Functional Testing
Session 2A System Testing

System-Level Test Bench Generation in a Co-Design Framework (Abstract)

L. Lavagno , Universit? di Udine
M. Rebaudengo , Politecnico di Torino
M. Violante , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Lajolo , NEC USA
pp. 25
Session 3A IDDQ Testing

LEAP: An Accurate Defect-Free IDDQ Estimator (Abstract)

Antoni Ferré , Universitat Polit?cnica de Catalunya
Joan Figueras , Universitat Polit?cnica de Catalunya
pp. 33
Session 6A Analog and Mixed-Signal Testing

Static and Dynamic On-Chip Test Response Evaluation Using a Two-Mode Comparator (Abstract)

M.J. Ohletz , Alcatel Microelectronics
G. Matarrese , Politecnico di Bari
D. de Venuto , Politecnico di Bari
pp. 47

Towards an ADC BIST Scheme Using the Histogram Test Technique (Abstract)

S. Bernard , University of Montpellier
M. Renovell , University of Montpellier
F. Azaïs , University of Montpellier
Y. Bertrand , University of Montpellier
pp. 53
Session 7A Fault Simulation and FPGA Testing

A Parameterizable Fault Simulator for Bridging Faults (Abstract)

Bernd Becker , Albert-Ludwigs-University
Martin Keim , Infineon Technologies AG
Piet Engelke , Albert-Ludwigs-University
pp. 63

Hierarchical Defect-Oriented Fault Simulation for Digital Circuits (Abstract)

W. Kuzmicz , Warsaw University of Technology
R. Ubar , Tallinn Technical University
E. Gramatová , Institute of Informatics at Bratislava
J. Raik , Tallinn Technical University
M. Lobur , State University ?Lvivska Politechnika?
T. Cibaková , Institute of Informatics at Bratislava
M. Blyzniuk , State University ?Lvivska Politechnika?
W. Pleskacz , Warsaw University of Technology
pp. 69
Session 7B Challenges in Deep Sub-Micron Testing

Test Challenges in Nanometer Technologies (Abstract)

Sanjay Sengupta , Intel Corporation
Rajesh Galivanche , Intel Corporation
Sandip Kundu , Intel Corporation
pp. 83

Current Testing Procedure for Deep Submicron Devices (Abstract)

Peter Cox , Alcatel Microelectronics
Dirk Merlier , Alcatel Microelectronics
Anton Chichkov , Alcatel Microelectronics
pp. 91
Session 9A High Level Test

Combining Symbolic and Genetic Techniques for Efficient Sequential Circuit Test Generation (Abstract)

E.M. Rudnick , University of Illinois at Urbana-Champaign
F. Fummi , Universit? di Verona
X. Yu , University of Illinois at Urbana-Champaign
M. Boschini , ST Microelectronics
pp. 105

How to Avoid Random Walks in Hierarchical Test Path Identification (Abstract)

Yiorgos Makris , University of California at San Diego
Alex Orailoglu , University of California at San Diego
Jamison Collins , University of California at San Diego
pp. 111
Session 9B Memory Testing

An Effective Distributed BIST Architecture for RAMs (Abstract)

Silvia Chiusano , Politecnico di Torino
Stefano di Carlo , Politecnico di Torino
Paolo Prinetto , Politecnico di Torino
Alfredo Benso , Politecnico di Torino
Giorgio di Natale , Politecnico di Torino
Monica Lobetti Bodoni , Siemens Information and Communication Networks S.p.A.
pp. 119

Compressed Bit Fail Maps for Memory Fail Pattern Classification (Abstract)

Ulf Lederer , Infineon Technologies
Thomas Hladschik , White Oak Semiconductor
Jörg Vollrath , White Oak Semiconductor
pp. 125
Session 10A BIST and Concurrent Testing

A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis (Abstract)

B. Rouzeyre , Universit? de Montpellier 2
D. Berthelot , Universit? de Montpellier 2
M.L. Flottes , Universit? de Montpellier 2
pp. 133

Low Cost Concurrent Test Implementation for Linear Digital Systems (Abstract)

Ismet Bayraktaroglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 140
Session 10B Board Testing
Session 11 BIST Architecture

Fast and Low-Area TPGs Based on T-Type Flip-Flops can be Easily Integrated to the Scan Path (Abstract)

Andrzej Hlawiczka , Silesian University of Technology
Adam Kristof , Silesian University of Technology
Tomasz Garbolino , Silesian University of Technology
pp. 161

CA-CSTP: A New BIST Architecture for Sequential Circuits (Abstract)

F. Corno , Politecnico di Torino
G. Squillero , Politecnico di Torino
M. Violante , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
pp. 167
Embedded Tutorials

Author Index (PDF)

pp. 181
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