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2013 18th IEEE European Test Symposium (ETS) (2013)
Avignon, France France
May 27, 2013 to May 30, 2013
ISBN: 978-1-4673-6376-1
TABLE OF CONTENTS
Papers

ETS 2013 Best Paper (PDF)

M. Violante , Politecnico di Torino, Torino, Italy
pp. 1

[Front cover] (PDF)

pp. 1
Papers

[Blank page] (PDF)

pp. 1

Foreword (PDF)

pp. 1

[Front cover] (PDF)

pp. 1

Outlook for many-core systems: Cloudy with a chance of virtualization (PDF)

Nikil Dutt , Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697-3435, USA
pp. 1

Robust optimization of test-architecture designs for core-based SoCs (PDF)

Sergej Deutsch , Department of Electrical and Computer Engineering Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering Duke University, Durham, NC 27708, USA
pp. 1-6

Computing detection probability of delay defects in signal line tsvs (PDF)

C. Metzler , LIRMM UMR 5506 - University of Montpellier 2/CNRS Montpellier, France
A. Todri-Sanial , LIRMM UMR 5506 - University of Montpellier 2/CNRS Montpellier, France
A. Bosio , LIRMM UMR 5506 - University of Montpellier 2/CNRS Montpellier, France
L. Dilillo , LIRMM UMR 5506 - University of Montpellier 2/CNRS Montpellier, France
P. Girard , LIRMM UMR 5506 - University of Montpellier 2/CNRS Montpellier, France
A. Virazel , LIRMM UMR 5506 - University of Montpellier 2/CNRS Montpellier, France
P. Vivet , CEA - LETI Grenoble, France
M. Belleville , CEA - LETI Grenoble, France
pp. 1-6

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers (PDF)

Christos Papameletis , Cadence Design Systems, Feldkirchen, Germany
Brion Keller , Cadence Design Systems Endicott, NY, USA
Vivek Chickermane , Cadence Design Systems Endicott, NY, USA
Erik Jan Marinissen , IMEC Leuven, Belgium
Said Hamdioui , TU Delft Delft, The Netherlands
pp. 1-6

Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software (PDF)

Giuseppe Di Guglielmo , University of Verona - Department of Computer Science
Davide Ferraretto , University of Verona - Department of Computer Science
Franco Fummi , University of Verona - Department of Computer Science
Graziano Pravadelli , University of Verona - Department of Computer Science
pp. 1-6

Experimental evaluation of thread distribution effects on multiple output errors in GPUs (PDF)

P. Rech , UFRGS, Universidade Federal do Rio Grande do Sul Porto Alegre, Brazil
C. Aguiar , UFRGS, Universidade Federal do Rio Grande do Sul Porto Alegre, Brazil
C. Frost , ISIS Rutherford Appleton Laboratories, Didcot, UK
L. Carro , UFRGS, Universidade Federal do Rio Grande do Sul Porto Alegre, Brazil
pp. 1-6

A software-based self test of CUDA Fermi GPUs (PDF)

Stefano Di Carlo , Politecnico di Torino Dipartimento di Automatica e Informatica Corso Duca degli Abruzzi 24, 1-10129, Torino, Italy
Giulio Gambardella , Politecnico di Torino Dipartimento di Automatica e Informatica Corso Duca degli Abruzzi 24, 1-10129, Torino, Italy
Marco Indaco , Politecnico di Torino Dipartimento di Automatica e Informatica Corso Duca degli Abruzzi 24, 1-10129, Torino, Italy
Ippazio Martella , Politecnico di Torino Dipartimento di Automatica e Informatica Corso Duca degli Abruzzi 24, 1-10129, Torino, Italy
Paolo Prinetto , Politecnico di Torino Dipartimento di Automatica e Informatica Corso Duca degli Abruzzi 24, 1-10129, Torino, Italy
Daniele Rolfo , Politecnico di Torino Dipartimento di Automatica e Informatica Corso Duca degli Abruzzi 24, 1-10129, Torino, Italy
Pascal Trotta , Politecnico di Torino Dipartimento di Automatica e Informatica Corso Duca degli Abruzzi 24, 1-10129, Torino, Italy
pp. 1-6

Scan pattern retargeting and merging with reduced access time (PDF)

Rafal Baranowski , ITI, University of Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany
Michael A. Kochte , ITI, University of Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany
Hans-Joachim Wunderlich , ITI, University of Stuttgart, Pfaffenwaldring 47, D-70569, Stuttgart, Germany
pp. 1-7

Utilizing circuit structure for scan chain diagnosis (PDF)

Wei-Hen Lo , Department of Computer Science, National Tsing Hua University HsinChu, Taiwan 300
Ang-Chih Hsieh , Department of Computer Science, National Tsing Hua University HsinChu, Taiwan 300
Chien-Ming Lan , Department of Computer Science, National Tsing Hua University HsinChu, Taiwan 300
Min-Hsien Lin , Department of Computer Science, National Tsing Hua University HsinChu, Taiwan 300
TingTing Hwang , Department of Computer Science, National Tsing Hua University HsinChu, Taiwan 300
pp. 1-6

A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing (PDF)

Saman Kiamehr , Karlsruhe Institute of Technology (KIT) 76131 Karlsruhe, Germany
Farshad Firouzi , Karlsruhe Institute of Technology (KIT) 76131 Karlsruhe, Germany
Mehdi B. Tahoori , Karlsruhe Institute of Technology (KIT) 76131 Karlsruhe, Germany
pp. 1-6

Adaptive quality binning for analog circuits (PDF)

Ender Yilmaz , Arizona State University
Sule Ozev , Arizona State University
Kenneth M. Butler , Texas Instruments
pp. 1-6

On combining alternate test with spatial correlation modeling in analog/RF ICs (PDF)

Ke Huang , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
Nathan Kupp , Department of Electrical Engineering, Yale University, New Haven, CT 06511
John M. Carulli , Texas Instruments Inc., 12500 TI Boulevard, MS 8741, Dallas, TX 75243
Yiorgos Makris , Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX 75080
pp. 1-6

Analytical modeling for EVM in OFDM transmitters including the effects of IIP3, I/Q imbalance, noise, AM/AM and AM/PM distortion (PDF)

Afsaneh Nassery , Arizona State University Electrical Engineering Tempe, AZ
Sule Ozev , Arizona State University Electrical Engineering Tempe, AZ
Mustapha Slamani , IBM Corp. Burlington, VT
pp. 1-6

Efficient system-level testing and adaptive tuning of MIMO-OFDM wireless transmitters (PDF)

S. Devarakond , Georgia Institute of Technology Atlanta, GA, USA
D. Banerjee , Georgia Institute of Technology Atlanta, GA, USA
A. Banerjee , Georgia Institute of Technology Atlanta, GA, USA
S. Sen , Intel Circuits and Systems Research Labs, Hillsboro, OR, USA
A. Chatterjee , Georgia Institute of Technology Atlanta, GA, USA
pp. 1-6

Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis (PDF)

Fangming Ye , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Zhaobo Zhang , Huawei Technologies Co. Ltd., Santa Clara, CA, USA
Krishnendu Chakrabarty , Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
Xinli Gu , Huawei Technologies Co. Ltd., Santa Clara, CA, USA
pp. 1-6

A mutual characterization based SAR ADC self-testing technique (PDF)

H.-J. Lin , Graduate Institute of Electronics Engineering
X.-L. Huang , Industrial Technology Research Institute, Hsinchu 310, Taiwan
J.-L. Huang , Graduate Institute of Electronics Engineering
pp. 1-6

Extracting device-parameter variations using a single sensitivity-configurable ring oscillator (PDF)

Yuma Higuchi , Dept. Information Systems Engineering, Osaka University, Japan
Ken-ichi Shinkai , Dept. Information Systems Engineering, Osaka University, Japan
Masanori Hashimoto , Dept. Information Systems Engineering, Osaka University, Japan
Rahul Rao , IBM Technology and Hardware Development Laboratory, India
Sani Nassif , IBM Austin Research Laboratory, USA
pp. 1-6

Current testing: Dead or alive? (PDF)

Hans Manhaeve , Ridgetop Europe
Adit Singh , Auburn University
Ralf Arnolc , Infineon
Davide Appello , ST Microelectronics
pp. 1

Reconciling the IC test and security dichotomy (PDF)

O. Sinanoglu , NYU Abu Dhabi
N. Karimi , Polytechnic Institute of NYU
J. Rajendran , Polytechnic Institute of NYU
R. Karri , Polytechnic Institute of NYU
Y. Jin , University of Central Florida
K. Huang , University of Texas at Dallas
Y. Makris , University of Texas at Dallas
pp. 1-6

Semiconductor failure modes and mitigation for critical systems embedded tutorial (PDF)

Hans Manhaeve , Ridgetop Europe Brugge, Belgium
Esko Mikkola , Ridgetop Group Inc. Tucson, Arizona USA
pp. 1-3

Approximate computing: An emerging paradigm for energy-efficient design (PDF)

Jie Han , Department of Electrical and Computer Engineering University of Alberta Edmonton, AB, Canada
Michael Orshansky , Department of Electrical and Computer Engineering University of Texas at Austin Austin, TX, USA
pp. 1-6

Error-correction schemes with erasure information for fast memories (PDF)

Samuel Evain , CEA, LIST, Saclay Nano-INNOV PC 172, 91191 Gif sur Yvette CEDEX, France
Valentin Gherman , CEA, LIST, Saclay Nano-INNOV PC 172, 91191 Gif sur Yvette CEDEX, France
pp. 1-6

Reducing power dissipation in memory repair for high defect densities (PDF)

Panagiota Papavramidou , TIMA (CNRS, Grenoble INP, UJF) Grenoble, France
Michael Nicolaidis , TIMA (CNRS, Grenoble INP, UJF) Grenoble, France
pp. 1-7

Analyzing resistive-open defects in SRAM core-cell under the effect of process variability (PDF)

Elena I. Vatajelu , LIRMM, Université de Montpellier II / CNRS 161 rue Ada - 34392 Montpellier Cedex 5, France
A. Bosio , LIRMM, Université de Montpellier II / CNRS 161 rue Ada - 34392 Montpellier Cedex 5, France
L. Dilillo , LIRMM, Université de Montpellier II / CNRS 161 rue Ada - 34392 Montpellier Cedex 5, France
P. Girard , LIRMM, Université de Montpellier II / CNRS 161 rue Ada - 34392 Montpellier Cedex 5, France
A. Todri , LIRMM, Université de Montpellier II / CNRS 161 rue Ada - 34392 Montpellier Cedex 5, France
A. Virazel , LIRMM, Université de Montpellier II / CNRS 161 rue Ada - 34392 Montpellier Cedex 5, France
N. Badereddine , Intel Mobile Communications 2600 route des Crêtes - 06560 Sophia-Antipolis, France
pp. 1-6

New test compression scheme based on low power BIST (PDF)

J. Tyszer , Poznań University of Technology 60-965 Poznań, Poland
M. Filipek , Poznań University of Technology 60-965 Poznań, Poland
G. Mrugalski , Mentor Graphics Corporation Wilsonville, OR 97070, USA
N. Mukherjee , Mentor Graphics Corporation Wilsonville, OR 97070, USA
J. Rajski , Mentor Graphics Corporation Wilsonville, OR 97070, USA
pp. 1-6

Novel approach to reduce power droop during scan-based logic BIST (PDF)

M. Omana , ARCES - DEI, University of Bologna Bologna, Italy
D. Rossi , ARCES - DEI, University of Bologna Bologna, Italy
F. Fuzzi , ARCES - DEI, University of Bologna Bologna, Italy
C. Metra , ARCES - DEI, University of Bologna Bologna, Italy
C. Tirumurti , Intel Corporation Santa Clara, CA
R. Galivache , Intel Corporation Santa Clara, CA
pp. 1-6

An error-detection and self-repairing method for dynamically and partially reconfigurable systems (PDF)

Matteo Sonza Reorda , Politecnico di Torino, Dipartimento di Automatica e Informatica Torino, Italy
Luca Sterpone , Politecnico di Torino, Dipartimento di Automatica e Informatica Torino, Italy
Anees Ullah , Politecnico di Torino, Dipartimento di Automatica e Informatica Torino, Italy
pp. 1-7

Run-time detection of hardware Trojans: The processor protection unit (PDF)

Jeremy Dubeuf , Grenoble INP Valence, France
David Hely , Grenoble INP Valence, France
Ramesh Karri , Polytechnic Institute of NewYork University Brooklyn, NY
pp. 1-6

Variability-aware and fault-tolerant self-adaptive applications for many-core chips (PDF)

Gilles Bizot , TIMA Laboratory, ARIS Team
Fabien Chaix , TIMA Laboratory, ARIS Team
Nacer-Eddine Zergainoh , TIMA Laboratory, ARIS Team
Michael Nicolaidis , TIMA Laboratory, ARIS Team
pp. 1

A minimum MSE sensor fusion algorithm with tolerance to multiple faults (PDF)

O. Sarbishei , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
A. Roshan Fekr , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
M. Janidarmian , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
B. Nahill , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
K. Radecka , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada
pp. 1

Bias temperature instability analysis in SRAM decoder (PDF)

Seyab Khan , Computer Engineering Laboratory Delft University of Technology Mekelweg 4, 2628 CD Delft, The Netherland
Said Hamdioui , Computer Engineering Laboratory Delft University of Technology Mekelweg 4, 2628 CD Delft, The Netherland
Halil Kukner , Kapeldreef 75, B-3001 Leuven, Belgium
Praveen Raghavan , Kapeldreef 75, B-3001 Leuven, Belgium
Francky Catthoor , Kapeldreef 75, B-3001 Leuven, Belgium
pp. 1

Generation of compact multi-cycle diagnostic test sets (PDF)

Irith Pomeranz , School of Electrical & Computer Eng. Purdue University W. Lafayette, IN 47907, U.S.A.
pp. 1

Aggresive scan chain masking for improved diagnosis of multiple scan chain failures (PDF)

Subhadip Kundu , Indian Institute of Technology Kharagpur, India
Santanu Chattopadhyay , Indian Institute of Technology Kharagpur, India
Indranil Sengupta , Indian Institute of Technology Kharagpur, India
Rohit Kapur , Synopsys Inc., Mountain View, California, USA
pp. 1

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information (PDF)

Seetal Potluri , Indian Institute of Technology Madras, Chennai - 600036, Tamilnadu, India
Satya Trinadh , Indian Institute of Technology Hyderabad. Yeddumailaram - 502205 Andhra Pradesh India
Roopashree Baskaran , National Institute of Technology Tiruchirapalli, Tiruchirappalli - 620015, Tamilnadu, India
Nitin Chandrachoodan , Indian Institute of Technology Madras, Chennai - 600036, Tamilnadu, India
V. Kamakoti , Indian Institute of Technology Madras, Chennai - 600036, Tamilnadu, India
pp. 1

Efficient minimization of test frequencies for linear analog circuits (PDF)

Mohand Bentobache , LAMOS Laboratory, University of Bejaia 06000, Algeria
Ahcene Bounceur , Lab-STICC Laboratory, University of Brest, 20, Avenue Victor Le Gorgeu 29238, Brest, France
Reinhardt Euler , Lab-STICC Laboratory, University of Brest, 20, Avenue Victor Le Gorgeu 29238, Brest, France
Yann Kieffer , LCIS Laboratory, University of Grenoble Alpes, 26900 Valence, France
Salvador Mir , TIMA Laboratory, 46, av. Félix Viallet, 38031 Grenoble, France
pp. 1

Implementing model redundancy in predictive alternate test to improve test confidence (PDF)

Haithem Ayari , LIRMM - CNRS/Univ. Montpellier 2 161 rue Ada, 34392 Montpellier, France
Florence Azais , LIRMM - CNRS/Univ. Montpellier 2 161 rue Ada, 34392 Montpellier, France
Serge Bernard , LIRMM - CNRS/Univ. Montpellier 2 161 rue Ada, 34392 Montpellier, France
Mariane Comte , LIRMM - CNRS/Univ. Montpellier 2 161 rue Ada, 34392 Montpellier, France
Vincent Kcrzerho , LIRMM - CNRS/Univ. Montpellier 2 161 rue Ada, 34392 Montpellier, France
Olivier Potin , LIRMM - CNRS/Univ. Montpellier 2 161 rue Ada, 34392 Montpellier, France
Michel Renovell , LIRMM - CNRS/Univ. Montpellier 2 161 rue Ada, 34392 Montpellier, France
pp. 1

RF BIST and test strategy for the receive part of an RF transceiver in CMOS technology (PDF)

Christophe Kelma , NXP Semiconductors, Campus Effiscience, 14460 Colombelles, France
Sebastien Darfeuille , NXP Semiconductors, Campus Effiscience, 14460 Colombelles, France
Andreas Neuburger , NXP Semiconductors, Mikron Weg 1, A-8101 Gratkorn, Austria
Andreas Lobnig , NXP Semiconductors, Mikron Weg 1, A-8101 Gratkorn, Austria
pp. 1

Hybrid 3D pre-bonding test framework design (PDF)

Unni Chandran , The Center for Advanced Computer Studies University of Louisiana at Lafayette
Dan Zhao , The Center for Advanced Computer Studies University of Louisiana at Lafayette
Rathish Jayabharathi , Intel Corporation Folsom, California
pp. 1

BIST architecture to detect defects in tsvs during pre-bond testing (PDF)

Daniel Arumi , Universitat Politècnica de Catalunya - Departament d'Enginyeria Electrònica Diagonal, 647, P9, 08028 Barcelona, Spain
Rosa Rodriguez-Montanes , Universitat Politècnica de Catalunya - Departament d'Enginyeria Electrònica Diagonal, 647, P9, 08028 Barcelona, Spain
Joan Figueras , Universitat Politècnica de Catalunya - Departament d'Enginyeria Electrònica Diagonal, 647, P9, 08028 Barcelona, Spain
pp. 1

Test generation for circuits with embedded memories using SMT (PDF)

Sarvesh Prabhu , Virginia Tech, Blacksburg USA
Michael S. Hsiao , Virginia Tech, Blacksburg USA
Loganathan Lingappan , Intel Corporation, USA
Vijay Gangaram , Intel Corporation, USA
pp. 1
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