The Community for Technology Leaders
2012 17th IEEE European Test Symposium (ETS) (2012)
Annecy France
May 28, 2012 to May 31, 2012
ISBN: 978-1-4673-0696-6
TABLE OF CONTENTS

Best paper (PDF)

pp. 1

Power-aware testing: The next stage (Abstract)

Xiaoqing Wen , Kyushu Institute of Technology, Iizuka, Fukuoka 820-8502, Japan
pp. 1

DfT support for launch and capture power reduction in launch-off-capture testing (PDF)

Samah Mohamed Saeed , Computer Science Department, New York University - Polytechnic Institute
Ozgur Sinanoglu , Computer Engineering Department New York University - Abu Dhabi
pp. 1-6

Cost and power efficient timing error tolerance in flip-flop based microprocessor cores (PDF)

Stefanos Valadimas , University of Athens, Dept. of Informatics and Telecommunications, 15784 Athens, Greece
Yiorgos Tsiatouhas , University of Ioannina, Dept. of Computer Science, 45110 Ioannina, Greece
Angela Arapoyanni , University of Athens, Dept. of Informatics and Telecommunications, 15784 Athens, Greece
pp. 1-6

Bandwidth-aware test compression logic for SoC designs (PDF)

Jakub Janicki , Pozna! University of Technology, 60-965 Poznań, Poland
Jerzy Tyszer , Pozna! University of Technology, 60-965 Poznań, Poland
Grzegorz Mrugalski , Mentor Graphics Corporation Wilsonville, OR 97070, USA
Janusz Rajski , Mentor Graphics Corporation Wilsonville, OR 97070, USA
pp. 1-6

On-line software-based self-test of the Address Calculation Unit in RISC processors (PDF)

P. Bernardi , Dipartimento di Automatica e Informatica, Politecnico di Torino - Torino, Italy
L. Ciganda , Dipartimento di Automatica e Informatica, Politecnico di Torino - Torino, Italy
M. de Carvalho , Dipartimento di Automatica e Informatica, Politecnico di Torino - Torino, Italy
M. Grosso , Dipartimento di Automatica e Informatica, Politecnico di Torino - Torino, Italy
J. Lagos-Benites , Dipartimento di Automatica e Informatica, Politecnico di Torino - Torino, Italy
E. Sanchez , Dipartimento di Automatica e Informatica, Politecnico di Torino - Torino, Italy
M. Sonza Reorda , Dipartimento di Automatica e Informatica, Politecnico di Torino - Torino, Italy
O. Ballan , STMicroelectronics, Agrate Brianza - Milano, Italy
pp. 1-6

Fast error detection through efficient use of hardwired resources in FPGAs (PDF)

Gabriel L. Nazar , Instituto de Informática, Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, Brazil
Luigi Carro , Instituto de Informática, Universidade Federal do Rio Grande do Sul - UFRGS, Porto Alegre, Brazil
pp. 1-6

Increasing autonomous fault-tolerant FPGA-based systems' lifetime (PDF)

Cristiana Bolchini , Dipartimento di Elettronica e Informazione, Politecnico di Milano
Antonio Miele , Dipartimento di Elettronica e Informazione, Politecnico di Milano
Chiara Sandionigi , Dipartimento di Elettronica e Informazione, Politecnico di Milano
pp. 1-6

Fault tolerant FPGA processor based on runtime reconfigurable modules (PDF)

Mihalis Psarakis , Department of Informatics, University of Piraeus, Greece
Andreas Apostolakis , Department of Informatics, University of Piraeus, Greece
pp. 1-6

BIST design for analog cell matching (PDF)

Candido Duarte , INESC TEC (formerly INESC Porto) and Faculty of Engineering, University of Porto, Microelectronics Students' Group, Faculty of Engineering, University of Porto, Campus da FEUP, Rua Dr. Roberto Frias, 378 4200-465 Porto, Portugal
Henrique Cavadas , INESC TEC (formerly INESC Porto) and Faculty of Engineering, University of Porto, Microelectronics Students' Group, Faculty of Engineering, University of Porto, Campus da FEUP, Rua Dr. Roberto Frias, 378 4200-465 Porto, Portugal
Pedro Coke , INESC TEC (formerly INESC Porto) and Faculty of Engineering, University of Porto, Microelectronics Students' Group, Faculty of Engineering, University of Porto, Campus da FEUP, Rua Dr. Roberto Frias, 378 4200-465 Porto, Portugal
Luis Malheiro , INESC TEC (formerly INESC Porto) and Faculty of Engineering, University of Porto, Microelectronics Students' Group, Faculty of Engineering, University of Porto, Campus da FEUP, Rua Dr. Roberto Frias, 378 4200-465 Porto, Portugal
Vitor Grade Tavares , INESC TEC (formerly INESC Porto) and Faculty of Engineering, University of Porto, Microelectronics Students' Group, Faculty of Engineering, University of Porto, Campus da FEUP, Rua Dr. Roberto Frias, 378 4200-465 Porto, Portugal
Pedro Guedes de Oliveira , INESC TEC (formerly INESC Porto) and Faculty of Engineering, University of Porto, Microelectronics Students' Group, Faculty of Engineering, University of Porto, Campus da FEUP, Rua Dr. Roberto Frias, 378 4200-465 Porto, Portugal
pp. 1-6

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs (PDF)

Asma Laraba , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
Salvador Mir , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
Herve Naudet , STMicroelectronics, 12 rue Jules Horowitz, 38000 Grenoble, France
Christophe Forel , STMicroelectronics, 12 rue Jules Horowitz, 38000 Grenoble, France
pp. 1-6

Characterization and handling of low-cost micro-architectural signatures in MPSoCs (PDF)

Armin Krieg , Institute for Technical Informatics Graz University of Technology, Austria
Johannes Grinschgl , Institute for Technical Informatics Graz University of Technology, Austria
Christian Steger , Institute for Technical Informatics Graz University of Technology, Austria
Reinhold Weiss , Institute for Technical Informatics Graz University of Technology, Austria
Andreas Genser , Design Center Graz, Infineon Technologies Austria AG
Holger Bock , Design Center Graz, Infineon Technologies Austria AG
Josef Haid , Design Center Graz, Infineon Technologies Austria AG
pp. 1-6

Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation (PDF)

Fabian Oboril , Chair of Dependable Nano Computing (CDNC), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
Mehdi B. Tahoori , Chair of Dependable Nano Computing (CDNC), Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany
pp. 1-6

OBT for settling error test of sampled-data systems using signal-dependent clocking (PDF)

Manuel J. Barragan , Instituto de Microlectrónica de Sevilla, Centro Nacional de Microelectrónica, Consejo Superior de Investigaciones Científicas (CSIC) and Universidad de Sevilla, Av. Américo Vespucio s/n, 41092 Sevilla, Spain
Gildas Leger , Instituto de Microlectrónica de Sevilla, Centro Nacional de Microelectrónica, Consejo Superior de Investigaciones Científicas (CSIC) and Universidad de Sevilla, Av. Américo Vespucio s/n, 41092 Sevilla, Spain
Jose L. Huertas , Instituto de Microlectrónica de Sevilla, Centro Nacional de Microelectrónica, Consejo Superior de Investigaciones Científicas (CSIC) and Universidad de Sevilla, Av. Américo Vespucio s/n, 41092 Sevilla, Spain
pp. 1-6

On-chip delay measurement circuit (PDF)

Abhishek Jain , STMicroelectronics Noida, India
Andrea Veggetti , STMicroelectronics Agrate, Italy
Dennis Crippa , STMicroelectronics Agrate, Italy
Pierluigi Rolandi , STMicroelectronics Agrate, Italy
pp. 1-6

On the detection of path delay faults by functional broadside tests (PDF)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
pp. 1-6

Functional test generation for hard to detect stuck-at faults using RTL model checking (PDF)

Mahesh Prabhu , Computer Engineering Research Center, University of Texas at Austin
Jacob A. Abraham , Computer Engineering Research Center, University of Texas at Austin
pp. 1-6

Exact stuck-at fault classification in presence of unknowns (PDF)

Stefan Hillebrecht , University of Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
Michael A. Kochte , ITI, University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany
Hans-Joachim Wunderlich , ITI, University of Stuttgart, Pfaffenwaldring 47, 70569 Stuttgart, Germany
Bernd Becker , University of Freiburg, Georges-Köhler-Allee 051, 79110 Freiburg, Germany
pp. 1-6

Memory reliability improvements based on maximized error-correcting codes (PDF)

Valentin Gherman , CEA, LIST, Saclay Nano-INNOV, PC 172, 91191 Gif sur Yvette CEDEX, France
Samuel Evain , CEA, LIST, Saclay Nano-INNOV, PC 172, 91191 Gif sur Yvette CEDEX, France
Yannick Bonhomme , CEA, LIST, Saclay Nano-INNOV, PC 172, 91191 Gif sur Yvette CEDEX, France
pp. 1-6

Time-division multiplexing for testing SoCs with DVS and multiple voltage islands (PDF)

Xrysovalantis Kavousianos , Dept. of Computer Science, University of Ioannina, Greece
Krishnendu Chakrabarty , Dept. of Electrical & Computer Engineering, Duke University, NC, USA
Arvind Jain , Texas Instruments (India) Pvt. Ltd., Bangalore, India
Rubin Parekhji , Texas Instruments (India) Pvt. Ltd., Bangalore, India
pp. 1-6

Combining dynamic slicing and mutation operators for ESL correction (PDF)

Urmas Repinski , Department of Computer Engineering, Tallinn University of Technology, Estonia
Hanno Hantson , Department of Computer Engineering, Tallinn University of Technology, Estonia
Maksim Jenihhin , Department of Computer Engineering, Tallinn University of Technology, Estonia
Jaan Raik , Department of Computer Engineering, Tallinn University of Technology, Estonia
Raimund Ubar , Department of Computer Engineering, Tallinn University of Technology, Estonia
Giuseppe Di Guglielmo , Department of Computer Science, University of Verona, Italy
Graziano Pravadelli , Department of Computer Science, University of Verona, Italy
Franco Fummi , Department of Computer Science, University of Verona, Italy
pp. 1-6

Multi-voltage aware resistive open fault modeling (PDF)

Mohamed Tagelsir Mohammadat , Electrical and Electronics Engineering Universiti Teknologi PETRONAS, Malaysia
Noohul Basheer Zain Ali , Electrical and Electronics Engineering Universiti Teknologi PETRONAS, Malaysia
Fawnizu Azmadi Hussin , Electrical and Electronics Engineering Universiti Teknologi PETRONAS, Malaysia
pp. 1-6

Indirect method for random jitter measurement on SoCs using critical path characterization (Abstract)

Jae Wook Lee , Intel Corp., Austin, TX, USA
Ji Hwan Chun , Intel Corp., Santa Clara, CA, USA
J. A. Abraham , Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX, USA
pp. 1-6

Adaptive testing of chips with varying distributions of unknown response bits (PDF)

Chandra K. H. Suresh , New York University, Abu Dhabi
Ozgur Sinanoglu , New York University, Abu Dhabi
Sule Ozev , Arizona State University
pp. 1-6

Toggle-masking scheme for x-filtering (PDF)

Abishek Ramdas , ECE Department, New York University - Polytechnic Institute
Ozgur Sinanoglu , Computer Engineering Department New York University - Abu Dhabi
pp. 1-6

Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test (PDF)

Alejandro Cook , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
Sybille Hellebrand , Institute of Electrical Engineering and Information Technology, University of Paderborn, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany
pp. 1-6

Multi-conditional SAT-ATPG for power-droop testing (PDF)

Alexander Czutro , Albert-Ludwigs-University Freiburg Georges-Köhler-Allee 051 79110 Freiburg, Germany
Matthias Sauer , Albert-Ludwigs-University Freiburg Georges-Köhler-Allee 051 79110 Freiburg, Germany
Ilia Polian , University of Passau, Innstraße 43 94032 Passau, Germany
Bernd Becker , Albert-Ludwigs-University Freiburg Georges-Köhler-Allee 051 79110 Freiburg, Germany
pp. 1-6

On the quality of test vectors for post-silicon characterization (PDF)

Matthias Sauer , Albert-Ludwigs-University Georges-Köhler-Allee 51 79110 Freiburg, Germany
Alexander Czutro , Albert-Ludwigs-University Georges-Köhler-Allee 51 79110 Freiburg, Germany
Bernd Becker , Albert-Ludwigs-University Georges-Köhler-Allee 51 79110 Freiburg, Germany
Ilia Polian , Faculty of Informatics and Mathematics, University of Passau, Innstr.43, 94032 Passau, Germany
pp. 1-6

Efficient system-level aging prediction (PDF)

Nadereh Hatami , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
Rafal Baranowski , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
Paolo Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 Torino TO, Italy
Hans-Joachim Wunderlich , University of Stuttgart, Institute of Computer Architecture and Computer Engineering, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
pp. 1-6

Diagnostic system based on support-vector machines for board-level functional diagnosis (PDF)

Zhaobo Zhang , Huawei Technologies, Co. Ltd., Santa Clara, CA
Xinli Gu , Huawei Technologies, Co. Ltd., Santa Clara, CA
Yaohui Xie , Huawei Technologies, Co. Ltd., Santa Clara, CA
Zhiyuan Wang , Huawei Technologies, Co. Ltd., Santa Clara, CA
Zhanglei Wang , Huawei Technologies, Co. Ltd., Santa Clara, CA
Krishnendu Chakrabarty , ECE Dept., Duke University, Durham, NC
pp. 1-6

Disturbance fault testing on various NAND flash memories (PDF)

Chih-Sheng Hou , Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320
Jin-Fu Li , Department of Electrical Engineering, National Central University, Jhongli, Taiwan 320
pp. 1

Functional analysis of circuits under timing variations (PDF)

Mehdi Dehbashi , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Gorschwin Fey , Institute of Space Systems, German Aerospace Center, 28359 Bremen, Germany
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
Anand Raghunathan , School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA
pp. 1

Enhanced wafer matching heuristics for 3-D ICs (PDF)

Vasilis F. Pavlidis , Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
Hu Xu , Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
Giovanni De Micheli , Integrated Systems Laboratory, EPFL, Lausanne, Switzerland
pp. 1

Defect analysis in power mode control logic of low-power SRAMs (PDF)

L. B. Zordan , LIRMM - Université Montpellier II / CNRS, France
A. Bosio , LIRMM - Université Montpellier II / CNRS, France
L. Dilillo , LIRMM - Université Montpellier II / CNRS, France
P. Girard , LIRMM - Université Montpellier II / CNRS, France
A. Todri , LIRMM - Université Montpellier II / CNRS, France
A. Virazel , LIRMM - Université Montpellier II / CNRS, France
N. Badereddine , Intel Mobile Communications, 2600, route des Crêtes - 06560, Sophia-Antipolis, France
pp. 1

Coupling-based resistive-open defects in TAS-MRAM architectures (PDF)

J. Azevedo , LIRMM - Université Montpellier 2 / CNRS - Montpellier, France
A. Virazel , LIRMM - Université Montpellier 2 / CNRS - Montpellier, France
A. Bosio , LIRMM - Université Montpellier 2 / CNRS - Montpellier, France
L. Dilillo , LIRMM - Université Montpellier 2 / CNRS - Montpellier, France
P. Girard , LIRMM - Université Montpellier 2 / CNRS - Montpellier, France
A. Todri , LIRMM - Université Montpellier 2 / CNRS - Montpellier, France
G. Prenat , CEA / SPINTEC - Grenoble, France
J. Alvarez-Herault , CROCUS Technology - Grenoble, France
K. Mackay , CROCUS Technology - Grenoble, France
pp. 1

On-chip temperature and voltage measurement for field testing (PDF)

Yukiya Miura , Tokyo Metropolitan University, Tokyo, Japan
Yasuo Sato , Kyushu Institute of Technology, Fukuoka, Japan
Yousuke Miyake , Kyushu Institute of Technology, Fukuoka, Japan
Seiji Kajihara , Kyushu Institute of Technology, Fukuoka, Japan
pp. 1

Impact of NBTI on analog components (PDF)

L V Zhengliang , Georgia Institute of Technology and Tsinghua University
Linda Milor , School of ECE, Georgia Institute of Technology
Shiyuan Yang , Dept. of Automation Tsinghua University
pp. 1

Through-Silicon-Via resistive-open defect analysis (PDF)

C. Metzler , LIRMM - University of Montpellier 2 / CNRS Montpellier, France
A. Todri , LIRMM - University of Montpellier 2 / CNRS Montpellier, France
A. Bosio , LIRMM - University of Montpellier 2 / CNRS Montpellier, France
L. Dilillo , LIRMM - University of Montpellier 2 / CNRS Montpellier, France
P. Girard , LIRMM - University of Montpellier 2 / CNRS Montpellier, France
A. Virazel , LIRMM - University of Montpellier 2 / CNRS Montpellier, France
pp. 1

Testing of digitally assisted adaptive analog/RF systems using tuning knob — Performance space estimation (PDF)

Aritra Banerjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
Shyam Devarakond , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
Shreyas Sen , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
Debashis Banerjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
Abhijit Chatterjee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
pp. 1

On-chip test comparison for protecting confidential data in secure ICs (PDF)

Jean Da Rolt , LIRMM (Université Montpellier II /CNRS UMR 5506) Montpellier, France
Giorgio Di Natale , LIRMM (Université Montpellier II /CNRS UMR 5506) Montpellier, France
Marie-Lise Flottes , LIRMM (Université Montpellier II /CNRS UMR 5506) Montpellier, France
Bruno Rouzeyre , LIRMM (Université Montpellier II /CNRS UMR 5506) Montpellier, France
pp. 1

Fault-Tolerant Algebraic Architecture for radiation induced soft-errors (PDF)

Fabio P. Itturriet , Instituto de Infrmática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Ronaldo R. Ferreira , Instituto de Infrmática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
Luigi Carro , Instituto de Infrmática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 1

Online detection and recovery of transient errors in front-end structures of microprocessors (PDF)

Syed Z. Shazli , Carbon Design Systems, Acton, MA, USA
Mehdi B. Tahoori , Faculty of Informatik (ITEC), Karlsruhe Institute of Technology, Karlsruhe, Germany
pp. 1

Test tool qualification through fault injection (PDF)

Q. Wang , EIS by Semcon AB, Sweden
A. Wallin , EIS by Semcon AB, Sweden
V. Izosimov , EIS by Semcon AB, Sweden
U. Ingelsson , EIS by Semcon AB, Sweden
Z. Peng , Linköping University, Sweden
pp. 1

A Software-Based Self-Test methodology for on-line testing of data TLBs (PDF)

G. Theodorou , Dept. of Informatics & Telecommunications, University of Athens, Greece
S. Chatzopoulos , Dept. of Informatics & Telecommunications, University of Athens, Greece
N. Kranitis , Dept. of Informatics & Telecommunications, University of Athens, Greece
A. Paschalis , Dept. of Informatics & Telecommunications, University of Athens, Greece
D. Gizopoulos , Dept. of Informatics & Telecommunications, University of Athens, Greece
pp. 1

Embedded synthetic instruments for Board-Level testing (PDF)

Artur Jutman , Testonica Lab OÜ, Tallinn, Estonia
Sergei Devadze , Tallinn Univ. of Technology, Dept. of Comp. Engineering, Tallinn, Estonia
Igor Aleksejev , Tallinn Univ. of Technology, Dept. of Comp. Engineering, Tallinn, Estonia
Thomas Wenzel , Goepel Electronic GmbH, Jena, Germany
pp. 1

Adaptive testing: Conquering process variations (PDF)

Ender Yilmaz , Arizona State University
Sule Ozev , Arizona State University
Ozgur Sinanoglu , New York University, Abu Dhabi
Peter Maxwell , Aptina, LLC
pp. 1-6

Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates (PDF)

F. Hapke , Mentor Graphics, Hamburg, Germany
J. Schloeffel , Mentor Graphics, Hamburg, Germany
pp. 1-6

Re-using chip level DFT at board level (PDF)

Xinli Gu , Huawei
Bill Eklow , Cisco
Martin Keim , Mentor Graphics
Jun Qian , AMD
Artur Jutman , Testonica
Krishnendu Chakrabarty , Duke University
Erik Larsson , Lund University
pp. 1

Funding project DIANA — Integrated diagnostics for the analysis of electronic failures in vehicles (PDF)

Piet Engelke , Infineon Technologies AG Am Campeon 1-12 D-85579 Neubiberg
Hermann Obermeir , Infineon Technologies AG Am Campeon 1-12 D-85579 Neubiberg
pp. 1

FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design (PDF)

Jaan Raik , Department of Computer Engineering Tallinn University of Technology, Estonia
pp. 1

Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale (PDF)

Marco Ottavi , Department of Electronic Engineering, University of Rome “Tor Vergata”, Rome, Italy
pp. 1

A robust metric for screening outliers from analogue product manufacturing tests responses (PDF)

Shaji Krishnan , Analytical Research Department, TNO, Zeist, The Netherlands
Hans G. Kerkhoff , Testable Design & Testing of Integrated Systems, University of Twente, CTIT, Enschede, The Netherlands
pp. 1-6
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