2013 18th IEEE European Test Symposium (ETS) (2011)
May 23, 2011 to May 27, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2011.51
Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality.
Parameter variations, Adaptive test, Delay test
S. Hellebrand, P. Maxwell, B. Becker, H. Wunderlich and I. Polian, "Towards Variation-Aware Test Methods," 2011 16th IEEE European Test Symposium (ETS), Trondheim, 2011, pp. 219-225.