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2013 18th IEEE European Test Symposium (ETS) (2011)
Trondheim, Norway
May 23, 2011 to May 27, 2011
ISSN: 1530-1877
ISBN: 978-0-7695-4433-5
pp: 205
ABSTRACT
Memory test optimization can significantly reduce test complexity, while retaining the quality of the test. In the presence of parasitic BL coupling, faults may only be detected by writing all possible coupling backgrounds (CBs) in the neighboring cells of the victim [2], [3]. However, using all possible CBs while testing for every fault consumes enormous test time, which can be significantly reduced, for the same fault coverage, if only limited required CBs are identified for each functional fault model (FFM). So far, no systematic approach has been proposed that identifies such limited required CBs, nor corresponding optimized memory tests generated that apply limited CBs [1]. Therefore, this paper presents a systematic approach to identify such limited CBs, and thereafter presents an optimized test, March BLC, which detects all static memory faults in the presence of BL coupling using only required CBs.
INDEX TERMS
Parasitic Bit Line coupling, Memory tests, SRAMs
CITATION
Zaid Al-Ars, Sandra Irobi, Said Hamdioui, "Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs", 2013 18th IEEE European Test Symposium (ETS), vol. 00, no. , pp. 205, 2011, doi:10.1109/ETS.2011.11
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