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2013 18th IEEE European Test Symposium (ETS) (2011)
Trondheim, Norway
May 23, 2011 to May 27, 2011
ISSN: 1530-1877
ISBN: 978-0-7695-4433-5
pp: 203
ABSTRACT
We propose a new test generation method for F-scan delay fault testing that uses standard full scan delay fault automatic test pattern generation (ATPG). This method shows that it is possible to generate test patterns fast for F-scannable register-transfer level (RTL) circuits by using currently well-developed and high-performance commercial ATPG tools for gate-level scan circuits.
INDEX TERMS
automatic test pattern generation, high-level testing, scan-based test
CITATION
Hideo Fujiwara, Marie Engelene J. Obien, Satoshi Ohtake, "F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG", 2013 18th IEEE European Test Symposium (ETS), vol. 00, no. , pp. 203, 2011, doi:10.1109/ETS.2011.61
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