2013 18th IEEE European Test Symposium (ETS) (2011)
May 23, 2011 to May 27, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2011.35
We present an approach for optimization of assertion placement in time-constrained HW/SW modules for detection of errors due to transient and intermittent faults. During the design phases, these assertions have to be inserted into the executable code and, hence, will always be executed with the corresponding code branches. As the result, they can significantly increase execution time of a module, in particular, contributing to a much longer execution of the worst case, and cause deadline misses. Assertions have different characteristics such as tightness (or "local error coverage") and execution latency. Taking into account these properties can increase efficiency of assertion checks in time-constrained embedded HW/SW modules. We have developed a design optimization framework, which (1) identifies candidate locations for assertions, (2) associates a candidate assertion to each location, and (3) selects a set of assertions in terms of performance degradation and assertion tightness. Experimental results have shown the efficiency of the proposed techniques.
soft errors, time-constrained embedded systems, executable assertions
Zebo Peng, Viacheslav Izosimov, Michele Lora, Masahiro Fujita, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi, "Optimization of Assertion Placement in Time-Constrained Embedded Systems", 2013 18th IEEE European Test Symposium (ETS), vol. 00, no. , pp. 171-176, 2011, doi:10.1109/ETS.2011.35