2013 18th IEEE European Test Symposium (ETS) (2011)
May 23, 2011 to May 27, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2011.21
High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power during at-speed delay fault testing represents an important issue. In the literature, several techniques have been proposed to reduce peak power consumption during at-speed LOC or LOS delay testing. On the other hand, some experiments have proved that too much test power reduction might lead to test escape and reliability problems. So, in order to avoid any yield loss and test escape due to power issues during test, test power has to map the power consumed during functional mode. In literature, some techniques have been proposed to apply test vectors that mimic functional operation from the switching activity point of view. The process consists of shifting-in a test vector (at low speed) and then applying several successive at-speed clock cycles before capturing the test response. In this paper, we propose a novel flow to determine the functional power to be used as test power (upper and lower) limits during at-speed delay testing. This flow is also used for comparison purpose between the above-mentioned test scheme and power consumption during the functional operation mode of a given circuit. The proposed methodology has been validated on an Intel MC8051 micro controller synthesized in a 65nm industrial technology.
At-speed delay fault testing, Power-aware Testing, Functional power
A. Bosio, M. Valka, M. De Carvalho, S. Pravossoudovitch, L. Dilillo, M. Sonza Reorda, E. Sanchez, P. Girard, A. Virazel, "A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing", 2013 18th IEEE European Test Symposium (ETS), vol. 00, no. , pp. 153-158, 2011, doi:10.1109/ETS.2011.21