2013 18th IEEE European Test Symposium (ETS) (2011)
May 23, 2011 to May 27, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2011.34
Verification is a major bottleneck in today's circuit and system design. This includes the tasks of error detection, error localization, and error correction in an implemented design as well as the analysis and avoidance of transient faults. For all those tasks, knowing for how long values of signals influence the system is important. In this paper, we propose a minimal and maximal latency measure for sequential circuits. This measure explains how long a circuit's state and outputs depend on input stimuli. Exact and heuristic algorithms are proposed to determine the measure. Experiments show that the measure provides insight into the behavior of circuit designs.
Latency, Debugging, Soft Error Analysis, Sequential Circuits, f
A. Sülflow, G. Fey and A. Finder, "Latency Analysis for Sequential Circuits," 2011 16th IEEE European Test Symposium (ETS), Trondheim, 2011, pp. 129-134.