The Community for Technology Leaders
2013 18th IEEE European Test Symposium (ETS) (2011)
Trondheim, Norway
May 23, 2011 to May 27, 2011
ISSN: 1530-1877
ISBN: 978-0-7695-4433-5
pp: 57-62
ABSTRACT
Process variations play a critical role in determining performance of scaled CMOS and other non-CMOS nanodevices. In this paper a power conscious post manufacture tuning technique is proposed for robust analog circuit fabrication with nanodevices in the presence of process variations. The response of the circuit to an optimized test signal is captured and using regression models, the proposed algorithm finds the best setting of tuning knobs for which the shifts in specifications from their nominal values are minimized in a power-aware manner. To demonstrate the proposed algorithm, a two stage Miller compensated operational amplifier is designed using carbon nanotube field effect transistors (CNFETs) and variability effects due to metallic CNT growth, diameter and chirality variations on the performance of the underlying circuits are studied. Suitable tuning knobs for the CNFET op-amp are identified based on the specifications to be tuned. Simulation results show that the proposed tuning algorithm enables overall yield improvement of 25.38% while minimizing power consumption of the tuned devices.
INDEX TERMS
CITATION
Abhijit Chatterjee, Subho Chatterjee, Aritra Banerjee, Azad Naeemi, "Power Aware Post-manufacture Tuning of Analog Nanocircuits", 2013 18th IEEE European Test Symposium (ETS), vol. 00, no. , pp. 57-62, 2011, doi:10.1109/ETS.2011.48
1658 ms
(Ver 3.3 (11022016))