2013 18th IEEE European Test Symposium (ETS) (2011)
May 23, 2011 to May 27, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2011.55
Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield, especially for larger stack sizes. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy. First, a analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Finally, these two parts are integrated to analyze the trade-off between yield improvement and its associated cost, the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, and at even lower cost. For example, for a stack size of six layers and a die yield of 85\%, a relative yield improvement of 82.46\% is obtained using one redundant layer, while this is 10.27\% with wafer matching. The additional cost due to redundancy pays off, the cost of producing a good 3D stacked memory chip reduces with 38.45\% when using layer redundancy and only with 10.27\% when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields.
3D stacked-IC, yield enhancement, memory redundancy, 3D memory
Said Hamdioui, Mottaqiallah Taouil, "Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories", 2013 18th IEEE European Test Symposium (ETS), vol. 00, no. , pp. 45-50, 2011, doi:10.1109/ETS.2011.55