2013 18th IEEE European Test Symposium (ETS) (2011)
May 23, 2011 to May 27, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2011.29
This paper proposes how the static linearity test method for DAC-ADC pairs using two low-quality signals can be optimized in terms of the used memory resources. The test is split into small segments so that the full histograms can be replaced by small ones. In the case of 16-bit ADC, the histogram memory requirement of an unoptimized algorithm is 131072 bytes while the proposed optimization cuts it down to 96 bytes. Test accuracy remains unchanged and the only cost of the memory optimization is 10 % increase in test time. In addition, it is proposed how the calculation algorithm can be modified so that floating-point arithmetics can be replaced by fixed-point arithmetics. This decreases the time used to calculate the INL and DNL estimates for each code by a factor of ten. The proposed optimizations are targeted for the self-testing of devices including DAC, ADC and some (limited) calculation and memory resources, e.g. micro controllers or system-on-chip devices.
algorithms, analog-digital conversion, didital-analog conversion, histograms, linearity, testing
E. Korhonen and J. Kostamovaara, "Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs," 2011 16th IEEE European Test Symposium (ETS), Trondheim, 2011, pp. 25-32.