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2011 16th IEEE European Test Symposium (ETS) (2011)
May 23, 2011 to May 27, 2011
ISSN: 1530-1877
ISBN: 978-1-4577-0483-3
pp: 177-182
Testing for small-delay defects (SDDs) becomes necessary as technology further scales. Traditional timing-unaware transition-delay fault (TDF) ATPGs are not adequate for detecting SDDs due to sensitization of short paths. Timing-aware ATPGs suffer from multiple paths sensitization limitation and significant test cost. In this paper, we present a critical fault-based methodology to generate high-quality SDD patterns. By focusing on critical faults, high quality original pattern repository could be generated applicably with n-detect ATPG. Novel pattern evaluation and selection method is presented to further minimize pattern count while maintaining the SDD detection ability. Finally, top-off ATPG is performed to ensure meeting the target fault coverage. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5X and saves approximately 80% CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, our pattern set detects equivalent or even more SDDs with significantly reduced pattern count.
Circuit faults, Automatic test pattern generation, Runtime, Benchmark testing, Delay
"Critical Fault-Based Pattern Generation for Screening SDDs", 2011 16th IEEE European Test Symposium (ETS), vol. 00, no. , pp. 177-182, 2011, doi:10.1109/ETS.2011.26
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