The Community for Technology Leaders
2010 15th IEEE European Test Symposium (2010)
Praha Czech Republic
May 24, 2010 to May 28, 2010
ISSN: 1530-1877
ISBN: 978-1-4244-5834-9
TABLE OF CONTENTS

Adaptive test directions (PDF)

Peter Maxwell , Aptina Imaging, San Jose, California
pp. 12-16

Production test challenges for highly integrated mobile phone SOCs — A case study (PDF)

Frank Poehl , Infineon Technologies AG, Neubiberg, Germany
Frank Demmerle , Infineon Technologies AG, Neubiberg, Germany
Juergen Alt , Infineon Technologies AG, Neubiberg, Germany
Hermann Obermeir , Infineon Technologies AG, Neubiberg, Germany
pp. 17-22

Test-architecture optimization for TSV-based 3D stacked ICs (PDF)

Brandon Noia , Dept. Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Sandeep Kumar Goel , Dept. Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Krishnendu Chakrabarty , Dept. Electrical and Computer Engineering, Duke University, Durham, NC 27708, USA
Erik Jan Marinissen , IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
Jouke Verbree , Dept. of Computer Engineering, Delft University of Technology, Mekelweg 4, 2628CD Delft, The Netherlands
pp. 24-29

A low-cost and scalable test architecture for multi-core chips (PDF)

Chun-Chuan Chi , Department of Electrical, Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013
Cheng-Wen Wu , Department of Electrical, Engineering, National Tsing Hua University, Hsinchu, Taiwan 30013
Jin-Fu Li , Department of Electrical, Engineering, National Central University, Jhongli, Taiwan 32001
pp. 30-35

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking (PDF)

Jouke Verbree , Delft University of Technology, Department of Computer Engineering, Mekelweg 4, 2628CD Delft, The Netherlands
Erik Jan Marinissen , IMEC vzw, 3D Integration Program, Kapeldreef 75, 3001 Leuven, Belgium
Philippe Roussel , IMEC vzw, 3D Integration Program, Kapeldreef 75, 3001 Leuven, Belgium
Dimitrios Velenis , IMEC vzw, 3D Integration Program, Kapeldreef 75, 3001 Leuven, Belgium
pp. 36-41

On the use of standard digital ATE for the analysis of RF signals (PDF)

N. Pous , LIRMM & Verigy, 34392 Montpellier, France
F. Azais , LIRMM, CNRS / Uni. Montpellier 2, 34392 Montpellier, France
L. Latorre , LIRMM, CNRS / Uni. Montpellier 2, 34392 Montpellier, France
J. Rivoir , Verigy Germany GmbH, 71034 Boeblingen, Germany
pp. 43-48

Sensors for built-in alternate RF test (PDF)

Louay Abdallah , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Fe´lix Viallet, 38031 Grenoble, France
Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Fe´lix Viallet, 38031 Grenoble, France
Christophe Kelma , NXP Semiconductors, 2 esplanade Anton Philips, Campus Effiscience, Colombelles BP20000, 14906 Caen, France
Salvador Mir , TIMA Laboratory (CNRS-Grenoble INP-UJF), 46 Av. Fe´lix Viallet, 38031 Grenoble, France
pp. 49-54

Low-cost signature test of RF blocks based on envelope response analysis (PDF)

Manuel J. Barragan , Instituto de Microelectrónica de Sevilla/Centro Nacional de Microelectrónica/Consejo Superior de Investigaciones Científicas (IMSE-CNM-CSIC)/Universidad de Sevilla, Ed. IMSE-CNM, Av. Americo Vespucio s/n, 41092 Sevilla, Spain
Rafaella Fiorelli , Instituto de Microelectrónica de Sevilla/Centro Nacional de Microelectrónica/Consejo Superior de Investigaciones Científicas (IMSE-CNM-CSIC)/Universidad de Sevilla, Ed. IMSE-CNM, Av. Americo Vespucio s/n, 41092 Sevilla, Spain
Diego Vazquez , Instituto de Microelectrónica de Sevilla/Centro Nacional de Microelectrónica/Consejo Superior de Investigaciones Científicas (IMSE-CNM-CSIC)/Universidad de Sevilla, Ed. IMSE-CNM, Av. Americo Vespucio s/n, 41092 Sevilla, Spain
Adoracion Rueda , Instituto de Microelectrónica de Sevilla/Centro Nacional de Microelectrónica/Consejo Superior de Investigaciones Científicas (IMSE-CNM-CSIC)/Universidad de Sevilla, Ed. IMSE-CNM, Av. Americo Vespucio s/n, 41092 Sevilla, Spain
Jose L. Huertas , Instituto de Microelectrónica de Sevilla/Centro Nacional de Microelectrónica/Consejo Superior de Investigaciones Científicas (IMSE-CNM-CSIC)/Universidad de Sevilla, Ed. IMSE-CNM, Av. Americo Vespucio s/n, 41092 Sevilla, Spain
pp. 55-60

Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging (PDF)

Ho Fai Ko , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
Nicola Nicolici , Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada
pp. 62-67

Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis (PDF)

Elena I. Vatajelu , Department of Electrical, Engineering, Universität Politécnica de Catalunya (UPC), Barcelona, Spam
Georgios Panagopoulos , Nanoelectromcs Research, Laboratory, Purdue University, West Lafayette, IN, USA
Kaushik Roy , Nanoelectromcs Research, Laboratory, Purdue University, West Lafayette, IN, USA
Joan Figueras , Department of Electrical, Engineering, Universität Politécnica de Catalunya (UPC), Barcelona, Spam
pp. 69-74

A low-cost built-in self-test scheme for an array of memories (PDF)

Yu-Jen Huang , Department of Electrical Engineering, National Central University, Jhongli, Taiwan
Che-Wei Chou , Department of Electrical Engineering, National Central University, Jhongli, Taiwan
Jin-Fu Li , Department of Electrical Engineering, National Central University, Jhongli, Taiwan
pp. 75-80

A two-layer SPICE model of the ATMEL TSTAC™ eFlash memory technology for defect injection and faulty behavior prediction (PDF)

P.-D. Mauroux , LIRMM ð University of Montpellier / CNRS, Montpellier, France
A. Virazel , LIRMM ð University of Montpellier / CNRS, Montpellier, France
A. Bosio , LIRMM ð University of Montpellier / CNRS, Montpellier, France
L. Dilillo , LIRMM ð University of Montpellier / CNRS, Montpellier, France
P. Girard , LIRMM ð University of Montpellier / CNRS, Montpellier, France
S. Pravossoudovitch , LIRMM ð University of Montpellier / CNRS, Montpellier, France
B. Godard , ATMEL, Rousset, France
G. Festes , ATMEL, Rousset, France
L. Vachez , ATMEL, Rousset, France
pp. 81-86

A transient error tolerant self-timed asynchronous architecture (PDF)

Masoud Zamani , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
Mehdi B. Tahoori , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
pp. 88-93

Multiple fault diagnosis in crossbar nano-architectures (PDF)

Navid Farazmand , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
Mehdi B. Tahoori , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
pp. 94-99

Full-circuit SPICE simulation based validation of dynamic delay estimation (PDF)

Ke Peng , ECE Department, University of Connecticut, Storrs, CT, USA
Yu Huang , Mentor Graphics, Wilsonville, OR, USA
Pinki Mallick , Mentor Graphics, Wilsonville, OR, USA
Wu-Tung Cheng , Mentor Graphics, Wilsonville, OR, USA
Mohammad Tehranipoor , ECE Department, University of Connecticut, Storrs, CT, USA
pp. 101-106

On estimation of NBTI-Induced delay degradation (PDF)

Mitsumasa Noda , Kyushu Institute of Technology, 680-4 Kawazu, Iizuka 820-8502 Japan
Seiji Kajihara , Kyushu Institute of Technology, 680-4 Kawazu, Iizuka 820-8502 Japan
Yasuo Sato , Kyushu Institute of Technology, 680-4 Kawazu, Iizuka 820-8502 Japan
Kohei Miyase , Kyushu Institute of Technology, 680-4 Kawazu, Iizuka 820-8502 Japan
Xiaoqing Wen , Kyushu Institute of Technology, 680-4 Kawazu, Iizuka 820-8502 Japan
Yukiya Miura , Tokyo Metropolitan University, 6-6 Asahigaoka, Hino, Tokyo 191-0065 Japan
pp. 107-111

Modified T-Flip-Flop based scan cell for RAS (PDF)

Raghavendra Adiga , Indian Institute of Science, Bangalore, India
Gandhi Arpit , Indian Institute of Science, Bangalore, India
Virendra Singh , Indian Institute of Science, Bangalore, India
Kewal K Saluja , University of Wisconsin-Madison, USA
Adit D. Singh , Auburn University, USA
pp. 113-118

Calibration-enabled scalable built-in current sensor compatible with very low cost ATE (PDF)

Sachin Dileep Dasnurkar , Computer Engineering Research Center, The University of Texas at Austin, Austin, TX 78712 U.S.A.
Jacob A. Abraham , Computer Engineering Research Center, The University of Texas at Austin, Austin, TX 78712 U.S.A.
pp. 119-124

Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs (PDF)

Jose L. Garcia-Gervacio , National Institute for Astrophysics, Optics and Electronics (INAOE), Puebla, México
Victor Champac , National Institute for Astrophysics, Optics and Electronics (INAOE), Puebla, México
pp. 126-131

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes (PDF)

R. Alves Fonseca , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
L. Dilillo , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
A. Bosio , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
P. Girard , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
S. Pravossoudovitch , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
A. Virazel , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
N. Badereddine , Infineon Technologies France 2600, route des Crêtes - 06560 Sophia-Antipolis, France
pp. 132-137

A reconfigurable online BIST for combinational hardware using digital neural networks (PDF)

S. Behdad Hosseini , CAD Laboratory, Electrical and Computer Engineering, School of Engineering Colleges, Campus 2, University of Tehran, 1450 North Amirabad, 14395-515 Tehran, Iran
Ali Shahabi , CAD Laboratory, Electrical and Computer Engineering, School of Engineering Colleges, Campus 2, University of Tehran, 1450 North Amirabad, 14395-515 Tehran, Iran
Hassan Sohofi , CAD Laboratory, Electrical and Computer Engineering, School of Engineering Colleges, Campus 2, University of Tehran, 1450 North Amirabad, 14395-515 Tehran, Iran
Zainalabedin Navabi , CAD Laboratory, Electrical and Computer Engineering, School of Engineering Colleges, Campus 2, University of Tehran, 1450 North Amirabad, 14395-515 Tehran, Iran
pp. 139-144

A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control (PDF)

Hyunjin Kim , Computer Engineering Research Center, The University of Texas at Austin, TX 78712
Jaeyong Chung , Computer Engineering Research Center, The University of Texas at Austin, TX 78712
Jacob A. Abraham , Computer Engineering Research Center, The University of Texas at Austin, TX 78712
Eonjo Byun , Samsung Electronics Co., Ltd. Hwasung-City, Korea
Cheol-Jong Woo , Samsung Electronics Co., Ltd. Hwasung-City, Korea
pp. 145-150

Constructing augmented time compactors (PDF)

Emil Gizdarski , Synopsys Inc., 700 East Middlefield Road, Mountain View, CA 94043
pp. 151-156

Predicting dynamic specifications of ADCs with a low-quality digital input signal (PDF)

Xiaoqin Sheng , CTIT-TDT Group, University of Twente, Enschede, the Netherlands
Vincent Kerzerho , CTIT-TDT Group, University of Twente, Enschede, the Netherlands
Hans G. Kerkhoff , CTIT-TDT Group, University of Twente, Enschede, the Netherlands
pp. 158-163

Test of embedded analog circuits based on a built-in current sensor (PDF)

Roman Mozuelos , Microelectronic Engineering Group, Dpt. TEISA, University of Cantabria, Santander, Spain
Yolanda Lechuga , Microelectronic Engineering Group, Dpt. TEISA, University of Cantabria, Santander, Spain
Mar Martinez , Microelectronic Engineering Group, Dpt. TEISA, University of Cantabria, Santander, Spain
Salvador Bracho , Microelectronic Engineering Group, Dpt. TEISA, University of Cantabria, Santander, Spain
pp. 164-169

Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications (PDF)

V. Malandruccolo , ETH Zurich, Switzerland
M. Ciappa , ETH Zurich, Switzerland
W. Fichtner , ETH Zurich, Switzerland
H. Rothleitner , Infineon Technologies, Villach, Austria
pp. 170-174

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs (PDF)

Daniel Tille , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Stephan Eggersgluss , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
Rene Krenz-Baath , Mentor Graphics Development (Deutschland) GmbH, 21079 Hamburg, Germany
Juergen Schloeffel , Mentor Graphics Development (Deutschland) GmbH, 21079 Hamburg, Germany
Rolf Drechsler , Institute of Computer Science, University of Bremen, 28359 Bremen, Germany
pp. 176-181

A distributed architecture to check global properties for post-silicon debug (PDF)

Erik Larsson , Linko¨pings universitet, Sweden
Bart Vermeulen , NXP Semiconductors, Netherlands
Kees Goossens , Eindhoven University of Technology, Netherlands
pp. 182-187

Automated conformance evaluation of SystemC designs using timed automata (PDF)

Paula Herber , Berlin Institute of Technology (TU Berlin), Germany
Marcel Pockrandt , Berlin Institute of Technology (TU Berlin), Germany
Sabine Glesner , Berlin Institute of Technology (TU Berlin), Germany
pp. 188-193

A software-based self-test methodology for system peripherals (PDF)

M. Grosso , Dipartimento di automatica e informatica, Politecnico di Torino, Torino, Italy
W. J. H. Perez , Grupo de Bionanoelectronica, Universidad del Valle, Cali, Colombia
D. Ravotto , Dipartimento di automatica e informatica, Politecnico di Torino, Torino, Italy
E. Sanchez , Dipartimento di automatica e informatica, Politecnico di Torino, Torino, Italy
M. Sonza Reorda , Dipartimento di automatica e informatica, Politecnico di Torino, Torino, Italy
J. Velasco Medina , Grupo de Bionanoelectronica, Universidad del Valle, Cali, Colombia
pp. 195-200

Microprocessor fault-tolerance via on-the-fly partial reconfiguration (PDF)

Stefano Di Carlo , Politecnico di Torino, Dipartimento di Automatica e Informatica, I-10129, Torino, Italy
Andrea Miele , Politecnico di Torino, Dipartimento di Automatica e Informatica, I-10129, Torino, Italy
Paolo Prinetto , Politecnico di Torino, Dipartimento di Automatica e Informatica, I-10129, Torino, Italy
Antonio Trapanese , Politecnico di Torino, Dipartimento di Automatica e Informatica, I-10129, Torino, Italy
pp. 201-206

Scan based speed-path debug for a microprocessor (PDF)

Jing Zeng , AMD Austin, TX, USA
Ruifeng Guo , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Wu-Tung Cheng , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Michael Mateja , AMD Austin, TX, USA
Jing Wang , AMD Austin, TX, USA
Kun-Han Tsai , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Ken Amstutz , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
pp. 207-212

An integrated flow for the design of hardened circuits on SRAM-based FPGAs (PDF)

Cristiana Bolchini , Dip. Elettronica e Informazione, Politecnico di Milano, Milano - Italy
Antonio Miele , Dip. Elettronica e Informazione, Politecnico di Milano, Milano - Italy
Chiara Sandionigi , Dip. Elettronica e Informazione, Politecnico di Milano, Milano - Italy
Niccolo Battezzati , Dip. di Automatica e Informatica, Politecnico di Torino, Torino - Italy
Luca Sterpone , Dip. di Automatica e Informatica, Politecnico di Torino, Torino - Italy
Massimo Violante , Dip. di Automatica e Informatica, Politecnico di Torino, Torino - Italy
pp. 214-219

Diagnosis of failing scan cells through orthogonal response compaction (PDF)

Brady Benware , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Grzegorz Mrugalski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Artur Pogiel , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Janusz Rajski , Mentor Graphics Corporation, Wilsonville, OR 97070, USA
Jedrzej Solecki , Poznań University of Technology, 60-965 Poznań, Poland
Jerzy Tyszer , Poznań University of Technology, 60-965 Poznań, Poland
pp. 221-226

An adaptive tester architecture for volume diagnosis (PDF)

P. Bernardi , Dipartimento di Automatica e Informatica - Politecnico di Torino, Torino (TO), Italy
M. Grosso , Dipartimento di Automatica e Informatica - Politecnico di Torino, Torino (TO), Italy
M. Sonza Reorda , Dipartimento di Automatica e Informatica - Politecnico di Torino, Torino (TO), Italy
pp. 227-232

Diagnosis of full open defects in interconnect lines with fan-out (PDF)

R. Rodriguez-Montanes , Universitat Politècnica de Catalunya, Departament d'Enginyeria Electrònica, Diagonal, 647, P9, 08028 Barcelona, Spain
D. Arumi , Universitat Politècnica de Catalunya, Departament d'Enginyeria Electrònica, Diagonal, 647, P9, 08028 Barcelona, Spain
J. Figueras , Universitat Politècnica de Catalunya, Departament d'Enginyeria Electrònica, Diagonal, 647, P9, 08028 Barcelona, Spain
S. Einchenberger , NXP Semiconductors, The Netherlands
C. Hora , NXP Semiconductors, The Netherlands
B. Kruseman , NXP Semiconductors, The Netherlands
pp. 233-238

Input test data volume reduction based on test vector chains (PDF)

Irith Pomeranz , School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A.
Sudhakar M. Reddy , Electrical & Computer Eng. Dept., University of Iowa, Iowa City, IA 52242, U.S.A.
pp. 240

On measurement uncertainty of ADC nonlinearities in oscillation-based test (PDF)

Peter Mrak , Jozef Stefan Institute, Ljubljana, Slovenia
Anton Biasizzo , Jozef Stefan Institute, Ljubljana, Slovenia
Franc Novak , Jozef Stefan Institute, Ljubljana, Slovenia
pp. 241

Fast simulation based testing of anti-tearing mechanisms for small embedded systems (PDF)

Johannes Loinig , Institute for Technical Informatics, Graz University of Technology, Graz, Austria
Christian Steger , Institute for Technical Informatics, Graz University of Technology, Graz, Austria
Reinhold Weiss , Institute for Technical Informatics, Graz University of Technology, Graz, Austria
Ernst Haselsteiner , NXP Semiconductors Austria GmbH, Gratkorn, Austria
pp. 242

New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism (PDF)

Xiao Zhang , Testable Design and Test of Integrated Systems Group, Centre of Telecommunication and Information Technology (CTIT), University of Twente, Enschede, the Netherlands
Hans G. Kerkhoff , Testable Design and Test of Integrated Systems Group, Centre of Telecommunication and Information Technology (CTIT), University of Twente, Enschede, the Netherlands
Bart Vermeulen , Distributed Systems Architectures Group, Research / Advanced Applications, NXP Semiconductors, Eindhoven, the Netherlands
pp. 243

Design and implementation of Automatic Test Equipment IP module (PDF)

S. Fransi , SFPe engineering, Munich, Germany
G. L. Farre , Electrical Engineering dep. (EEL), Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
L. G. Deiros , Electrical Engineering dep. (EEL), Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
S. B. Manich , Electrical Engineering dep. (EEL), Universitat Politècnica de Catalunya (UPC), Barcelona, Spain
pp. 244

Add-on blocks and algorithms for improving stimulus compression (PDF)

Nader Alawadhi , Math & Computer Science Department, Kuwait University, Safat, Kuwait 13060
Ozgur Sinanoglu , Math & Computer Science Department, Kuwait University, Safat, Kuwait 13060
Mohammed Al-Mulla , Math & Computer Science Department, Kuwait University, Safat, Kuwait 13060
pp. 245

Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization (PDF)

Sezer Goren , Dept. of Computer Engineering, Bahçesehir University, Istanbul, Turkey
H. Fatih Ugurdag , Dept. of Computer Engineering, Bahçesehir University, Istanbul, Turkey
Okan Palaz , Dept. of Computer Engineering, Bahçesehir University, Istanbul, Turkey
pp. 246

Hybrid test application in hybrid delay scan design (PDF)

Yuki Yoshikawa , Graduate School of Information Sciences, Hiroshima City University, Hiroshima, 731-3194, Japan
Tomomi Nuwa , Semiconductor Co., Panasonic Corp., Kyoto 617-8520, Japan
Hideyuki Ichihara , Graduate School of Information Sciences, Hiroshima City University, Hiroshima, 731-3194, Japan
Tomoo Inoue , Graduate School of Information Sciences, Hiroshima City University, Hiroshima, 731-3194, Japan
pp. 247

Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints (PDF)

Sobeeh Almukhaizim , Computer Engineering Department, Kuwait University
Sara Bunian , Computer Engineering Department, Kuwait University
Ozgur Sinanoglu , Math & Computer Science Department, Kuwait University
pp. 248

Test power reduction in compression-based reconfigurable scan architectures (PDF)

Sobeeh Almukhaizim , Computer Engineering Department, Kuwait University
Mohammad Gh. Mohammad , Computer Engineering Department, Kuwait University
Mohammad Khajah , Department of Advanced Systems, Kuwait Institute for Scientific Research
pp. 249

Multivariate model for test response analysis (PDF)

Shaji Krishnan , Analytical Research Department TNO, Zeist, The Netherlands
Hans G. Kerkhoff , CTIT-TDT, University of Twente, Enschede, The Netherlands
pp. 250

Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA (PDF)

G. Canivet , TIMA Laboratory, (Grenoble INP, UJF, CNRS)
P. Maistn , TIMA Laboratory, (Grenoble INP, UJF, CNRS)
R. Leveugle , TIMA Laboratory, (Grenoble INP, UJF, CNRS)
F. Valette , DGA/CELAR
J. Clediere , CESTI/CEA-LETI
M. Renaudin , Tiempo
pp. 251

Evaluation of concurrent error detection techniques on the Advanced Encryption Standard (PDF)

K. Bousselam , LIRMM (Université Montpellier II / CNRS UMR 5506), Montpellier, France
G. Di Natale , LIRMM (Université Montpellier II / CNRS UMR 5506), Montpellier, France
M-L. Flottes , LIRMM (Université Montpellier II / CNRS UMR 5506), Montpellier, France
B. Rouzeyre , LIRMM (Université Montpellier II / CNRS UMR 5506), Montpellier, France
pp. 252

Algorithm-based fault tolerance for many-core architectures (PDF)

Claus Braun , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
Hans-Joachim Wunderlich , Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart, Germany
pp. 253

A diagnostic test generation system and a coverage metric (PDF)

Yu Zhang , Auburn University, Department of Electrical and Computer Engineering, Auburn, AL 36849, USA
Vishwani D. Agrawal , Auburn University, Department of Electrical and Computer Engineering, Auburn, AL 36849, USA
pp. 254

A shared BIST optimization methodology for memory test (PDF)

Lilia Zaourar , G-SCOP Laboratory, Grenoble INP, 46 Avenue Felix Viallet, 38031 cedexl, Grenoble, France
Jihane Alami Chentoufi , G-SCOP Laboratory, Grenoble INP, 46 Avenue Felix Viallet, 38031 cedexl, Grenoble, France
Yann Kieffer , G-SCOP Laboratory, Grenoble INP, 46 Avenue Felix Viallet, 38031 cedexl, Grenoble, France
Arnaud Wenzel , ST Microelectronics 850, rue Jean Monnet, 38926 Crolles, France
Frederic Grandvaux , ST Microelectronics 850, rue Jean Monnet, 38926 Crolles, France
pp. 255

Pipelined parallel test structure for mixed-signal SoCs (PDF)

Yang Jin , Department of Automation, Tsinghua University, Beijing, China, 100084
Hong Wang , Department of Automation, Tsinghua University, Beijing, China, 100084
Zhengliang Lv , Department of Automation, Tsinghua University, Beijing, China, 100084
Shiyuan Yang , Department of Automation, Tsinghua University, Beijing, China, 100084
pp. 256

Setting test conditions for improving SRAM reliability (PDF)

R. Alves Fonseca , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
L. Dilillo , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
A. Bosio , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
P. Girard , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
S. Pravossoudovitch , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
A. Virazel , LIRMM Université de Montpellier II / CNRS 161, rue Ada - 34392 Montpellier Cedex 5, France
N. Badereddine , Infineon Technologies France, 2600, route des Crêtes - 06560 Sophia-Antipolis, France
pp. 257

Configurable fault-tolerant link for inter-die communication in 3D on-chip networks (PDF)

Vladimir Pasca , TIMA Laboratory, Grenoble, France
Lorena Anghel , TIMA Laboratory, Grenoble, France
Claudia Rusu , TIMA Laboratory, Grenoble, France
Mounir Benabdenbi , TIMA Laboratory, Grenoble, France
pp. 258

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach (PDF)

Jaynarayan T Tudu , Indian Institute of Science, Bangalore, India
Erik Larsson , Linköping Universitet, Linköping, Sweden
Virendra Singh , Indian Institute of Science, Bangalore, India
Hideo Fujiwara , Nara Institute of Science and Technology, Nara, Japan
pp. 259

Test pattern selection to optimize delay test quality with a limited size of test set (PDF)

Michiko Inoue , Graduate School of Information Science, Nara Institute of Science and Technology
Akira Taketani , Graduate School of Information Science, Nara Institute of Science and Technology
Tomokazu Yoneda , Graduate School of Information Science, Nara Institute of Science and Technology
Hiroshi Iwata , Graduate School of Information Science, Nara Institute of Science and Technology
Hideo Fujiwara , Graduate School of Information Science, Nara Institute of Science and Technology
pp. 260

Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy (PDF)

Gabriel de M. Borges , Universidade Federal do Rio Grande do Sul
Luiz F. Goncalves , Universidade Federal do Rio Grande do Sul
Tiago R. Balen , Universidade Federal do Rio Grande do Sul
Marcelo S. Lubaszewski , Universidade Federal do Rio Grande do Sul
pp. 261

Current-based testable design of level shifters in liquid crystal display drivers (PDF)

Masaki Hashizume , Institute of Technology and Science, The Univ. of Tokushima, Tokushima, Japan
Kazuya Nakaminami , Institute of Technology and Science, The Univ. of Tokushima, Tokushima, Japan
Hiroyuki Yotsuyanagi , Institute of Technology and Science, The Univ. of Tokushima, Tokushima, Japan
Yukinori Nakajima , Sharp Co. Ltd, Tenri, Nara, Japan
Kozo Kinoshita , Faculty of Informatics, Osaka Gakuin University, Suita, Osaka, Japan
pp. 262

A multi-mode MEMS sensor design to support system test and health & usage monitoring applications (PDF)

Z. Xu , Department of Engineering, Lancaster University Lancaster, LA1 4YR, UK
A. Richardson , Department of Engineering, Lancaster University Lancaster, LA1 4YR, UK
L. Li , Institute for System Level Integration, Livingston, EH54 7EG, UK
M. Begbie , Institute for System Level Integration, Livingston, EH54 7EG, UK
D. Koltsov , BREC Solutions, Lancaster, LA1 2DG, UK
C. H. Wang , School of Engineering & Physical Sciences, Heriot-Watt University, Edinburgh, EH14 4AS, UK
pp. 263

A new built-in IDDQ testing method using programmable BICS (PDF)

Samed Maltabas , Department of Electrical and Computer Engineering, University of Massachusetts Lowell, Lowell, MA, USA
Osman Kubilay Ekekon , Department of Electrical and Computer Engineering, University of Massachusetts Lowell, Lowell, MA, USA
Martin Margala , Department of Electrical and Computer Engineering, University of Massachusetts Lowell, Lowell, MA, USA
pp. 264

Defect filter for alternate RF test (PDF)

Haralampos-G. Stratigopoulos , TIMA Laboratory (CNRS-INP Grenoble-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
Salvador Mir , TIMA Laboratory (CNRS-INP Grenoble-UJF), 46 Av. Félix Viallet, 38031 Grenoble, France
Erkan Acar , Duke University, Electrical & Computer Engineering Dept., Durham, NC 27708, USA
Sule Ozev , Arizona State University, Electrical Engineering Dept., Tempe, AZ 85287, USA
pp. 265-270
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