The Community for Technology Leaders
2013 18th IEEE European Test Symposium (ETS) (2007)
Freiburg, Germany
May 20, 2007 to May 24, 2007
ISSN: 1530-1877
ISBN: 0-7695-2827-9
TABLE OF CONTENTS
Introduction

Foreword (PDF)

pp. ix
Plenary Presentations
Fault and Defect Diagnosis

Adaptive Debug and Diagnosis without Fault Dictionaries (Abstract)

Hans-Joachim Wunderlich , Universitat Stuttgart, Germany
Stefan Holst , Universitat Stuttgart, Germany
pp. 7-12

DERRIC: A Tool for Unified Logic Diagnosis (Abstract)

A. Virazel , Universite Montpellier II/CNRS, France
A. Bosio , Universite Montpellier II/CNRS, France
S. Pravossoudovitch , Universite Montpellier II/CNRS, France
C. Landrault , Universite Montpellier II/CNRS, France
P. Girard , Universite Montpellier II/CNRS, France
A. Rousset , Universite Montpellier II/CNRS, France
pp. 13-20
Mixed Signal DFT and Test

A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul, Brazil
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul, Brazil
Pascal Nouet , Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier, France
Erik Schuler , Universidade Federal do Rio Grande do Sul, Brazil
pp. 21-28
NoC Testing

Test Configurations for Diagnosing Faulty Links in NoC Switches (Abstract)

Jaan Raik , Tallinn University of Technology, Estonia
Vineeth Govind , Tallinn University of Technology, Estonia
Raimund Ubar , Tallinn University of Technology, Estonia
pp. 29-34

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints (Abstract)

Hideo Fujiwara , Nara Institute of Science and Technology, Japan
Fawnizu Azmadi Hussin , Nara Institute of Science and Technology, Japan
Tomokazu Yoneda , Nara Institute of Science and Technology, Japan
pp. 35-42
Advances in RF Test

FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests (Abstract)

Roland May , Infineon Technologies AG, Germany
Ivo Koren , Infineon Technologies AG, Germany
Frank Demmerle , Infineon Technologies AG, Germany
Martin Kaibel , Infineon Technologies AG, Germany
Sebastian Sattler , Infineon Technologies AG, Germany
pp. 43-48

Digital Generation of Signals for Low Cost RF BIST (Abstract)

Luigi Carro , Universidade Federal do Rio Grande do Sul, Brazil
Marcelo Negreiros , Universidade Federal do Rio Grande do Sul, Brazil
Altamiro A. Susin , Universidade Federal do Rio Grande do Sul, Brazil
pp. 49-54

Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives (Abstract)

Rene Jonker , NXP Semiconductors, The Netherlands
Leon van de Logt , NXP Semiconductors, The Netherlands
Shaji Krishnan , NXP Semiconductors, The Netherlands
pp. 55-62
Diagnosis and Debug

Communication-Centric SoC Debug Using Transactions (Abstract)

Kees Goossens , NXP Semiconductors Research, The Netherlands; Technical University Delft, The Netherlands
Bart Vermeulen , NXP Semiconductors Research, The Netherlands
Remco van Steeden , Technical University of Twente, The Netherlands
Martijn Bennebroek , Philips Research, The Netherlands
pp. 69-76
Simulation and Verification

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories (Abstract)

C. Landrault , Universite de Montpellier II/CNRS, France
A. Virazel , Universite de Montpellier II/CNRS, France
J.-M. Daga , ATMEL Rousset, France
O. Ginez , Universite de Montpellier II/CNRS, France; ATMEL Rousset, France
P. Girard , Universite de Montpellier II/CNRS, France
S. Pravossoudovitch , Universite de Montpellier II/CNRS, France
pp. 77-84
Memory Test

PPM Reduction on Embedded Memories in System on Chip (Abstract)

Javier Jimenez , Design of Systems on Silicon (DS2), Spain
Jose Calero , Design of Systems on Silicon (DS2), Spain
Said Hamdioui , Delft University of Technology, The Netherlands
Zaid Al-Ars , Delft University of Technology, The Netherlands
pp. 85-90

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy (Abstract)

Sybille Hellebrand , University of Paderborn, Germany
Hans-Joachim Wunderlich , University of Stuttgart, Germany
Philipp Ohler , University of Paderborn, Germany
pp. 91-96

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs (Abstract)

M. Bastian , Infineon Technologies, France
P. Girard , Universite de Montpellier II/CNRS, France
A. Ney , Universite de Montpellier II/CNRS, France
C. Landrault , Universite de Montpellier II/CNRS, France
A. Virazel , Universite de Montpellier II/CNRS, France
S. Pravossoudovitch , Universite de Montpellier II/CNRS, France
pp. 97-104
On-Line Testing and Self-Test

A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus (Abstract)

R.J.T. Bunyan , QinetiQ, UK
A. Richardson , Lancaster University, UK
K. Georgopoulos , Lancaster University, UK
Z. Xu , Lancaster University, UK
N. Dumas , Lancaster University, UK
pp. 105-110

Selecting Power-Optimal SBST Routines for On-Line Processor Testing (Abstract)

A. Paschalis , University of Athens, Greece
N. Kranitis , University of Athens, Greece
D. Gizopoulos , University of Piraeus, Greece
A. Merentitis , University of Athens, Greece
pp. 111-116

Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors (Abstract)

Tomoo Inoue , Hiroshima City University, Japan
Hideyuki Ichihara , Hiroshima City University, Japan
Takashi Fujii , Hiroshima City University, Japan
pp. 117-124
Fault Grading and Test Quality

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression (Abstract)

Krishnendu Chakrabarty , Duke University, USA
Zhanglei Wang , Duke University, USA
Michael Bienek , Advanced Micro Devices, USA
pp. 125-130

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs (Abstract)

Sergei Devadze , Tallinn University of Technology, Estonia
Jaan Raik , Tallinn University of Technology, Estonia
Raimund Ubar , Tallinn University of Technology, Estonia
Artur Jutman , Tallinn University of Technology, Estonia
pp. 131-136

Computation and Application of Absolute Dominators in Industrial Designs (Abstract)

Rene Krenz-Baath , NXP Semiconductors, Germany
Andreas Glowatz , NXP Semiconductors, Germany
Juergen Schloeffel , NXP Semiconductors, Germany
pp. 137-144
Diagnosis and Yield Improvement

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement (Abstract)

Janusz Rajski , Mentor Graphics Corporation, USA
Brady Benware , Mentor Graphics Corporation, USA
Huaxing Tang , Mentor Graphics Corporation, USA
Martin Keim , Mentor Graphics Corporation, USA
Sharma Manish , Mentor Graphics Corporation, USA
pp. 145-150

Diagnostic Test Generation Based on Subsets of Faults (Abstract)

Sudhakar M. Reddy , University of Iowa, USA
Irith Pomeranz , Purdue University, USA
pp. 151-158
Single Event Upsets

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs (Abstract)

L. Sterpone , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
pp. 159-164

System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies (Abstract)

M.I. Erigson , Universidade Federal do Rio Grande do Sul, Brazil
C.A. Lisboa , Universidade Federal do Rio Grande do Sul, Brazil
L. Carro , Universidade Federal do Rio Grande do Sul, Brazil
pp. 165-172
Delay and Performance Test

Automatic Generation of Instructions to Robustly Test Delay Defects in Processors (Abstract)

Ramtilak Vemu , The University of Texas at Austin, USA
Jacob A. Abraham , The University of Texas at Austin, USA
Sankar Gurumurthy , The University of Texas at Austin, USA
Daniel G. Saab , Case Western Reserve University
pp. 173-178

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores (Abstract)

M. Grosso , Politecnico di Torino, Italy
P. Bernardi , Politecnico di Torino, Italy
E. Sanchez , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 179-184

Purely Digital BIST for Any PLL or DLL (Abstract)

Aubin Roy , LogicVision, Inc.
Stephen Sunter , LogicVision, Inc.
pp. 185-192
Embedded Tutorials

System-in-Package, a Combination of Challenges and Solutions (Abstract)

M. Renovell , LIRMM, University of Montpellier/CNRS, France
P. Cauvet , NXP Semiconductors, France
S. Bernard , LIRMM, University of Montpellier/CNRS, France
pp. 193-199

Embedded Tutorial: IC Test Cost Benchmarking (PDF)

Klaus Luther , Infineon Technologies AG, Germany
pp. 200

Wafer Level Reliability Screens (PDF)

Peter Maxwell , Micron Technology
pp. 201

Embedded Tutorial on Low Power Test (Abstract)

Xiaoqing Wen , Kyushu Institute of Technology, Japan
Nicola Nicolici , McMaster University, Canada
pp. 202-210
ETS06 Best Paper

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC (Abstract)

M. Comte , LIRMM, University of Montpellier/CNRS, France
P. Cauvet , Philips France Semiconducteurs
M. Renovell , LIRMM, University of Montpellier/CNRS, France
F. Azais , LIRMM, University of Montpellier/CNRS, France
S. Bernard , LIRMM, University of Montpellier/CNRS, France
V. Kerzerho , LIRMM, University of Montpellier/CNRS, France; Philips France Semiconducteurs
pp. 211-216
Author Index

Author Index (PDF)

pp. 217
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