May 20, 2007 to May 24, 2007
Sankar Gurumurthy , The University of Texas at Austin, USA
Ramtilak Vemu , The University of Texas at Austin, USA
Jacob A. Abraham , The University of Texas at Austin, USA
Daniel G. Saab , Case Western Reserve University
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ETS.2007.13
We present a technique for generating instruction sequences to test a processor functionally. We target delay defects with this technique using an ATPG engine to generate delay tests locally, a verification engine to map the tests globally, and a feedback mechanism that makes the entire procedure faster. We demonstrate nearly 96% coverage of delay faults with the instruction sequences generated. These instruction sequences can be loaded into the cache to test the processor functionally.
Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab, "Automatic Generation of Instructions to Robustly Test Delay Defects in Processors", ETS, 2007, 2013 18th IEEE European Test Symposium (ETS), 2013 18th IEEE European Test Symposium (ETS) 2007, pp. 173-178, doi:10.1109/ETS.2007.13