The Community for Technology Leaders
2013 18th IEEE European Test Symposium (ETS) (2006)
Southampton, United Kingdom
May 21, 2006 to May 21, 2006
ISSN: 1530-1877
ISBN: 0-7695-2566-0
TABLE OF CONTENTS
Introduction

Foreward (PDF)

pp. ix
Plenary Presentations

Living with Failure: Lessons from Nature? (PDF)

Steve Furber , University of Manchester, UK
pp. 4-8
Delay Fault Testing

Low Cost Launch-on-Shift Delay Test with Slow Scan Enable (Abstract)

Gefu Xu , Auburn University, USA
Adit D. Singh , Auburn Univesity, USA
pp. 9-14

Dynamic Voltage Scaling Aware Delay Fault Testing (Abstract)

Peter Harrod , ARM. Ltd.
Noohul Basheer Zain Ali , University of Southampton, UK
Bashir M Al-Hashimi , University of Southampton, UK
Mark Zwolinski , University of Southampton, UK
pp. 15-20

Enhancing Delay Fault Coverage through Low Power Segmented Scan (Abstract)

Sudhakar M. Reddy , University of Iowa, USA
Bashir M. Al-Hashimi , University of Southampton, UK
Irith Pomeranz2, Pomeranz , Purdue University, USA
Zhuo Zhang , University of Iowa, USA
Janusz Rajski , Mentor Graphics Corp., USA
pp. 21-28
Single-Event Upsets

Single-Event Upset Analysis and Protection in High Speed Circuits (Abstract)

Stefano Di Carlo , Politecnico di Torino, Italy
Pejman Lotfi-Kamran , University of Tehran, Iran
Alfredo Benso , Politecnico di Torino, Italy
Mohammad Hosseinabady , University of Tehran, Iran
Paolo Prinetto , Politecnico di Torino, Italy
Giorgio Di Natale , Politecnico di Torino, Italy
pp. 29-34

Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study (Abstract)

Soumendu Bhattacharya , Georgia Institute of Technology, USA
Maryam Ashouei , Georgia Instititute of Technology, USA
Abhijit Chatterjee , Georgia Institute of Technology, USA
pp. 35-42
Memory Testing - 1

Minimal March Tests for Dynamic Faults in Random Access Memories (Abstract)

Y. Zorian , Virage Logic, Armenia
V.A. Vardanian , Virage Logic, Armenia
G. Harutunyan , Virage Logic, Armenia
pp. 43-48

A 22n March Test for Realistic Static Linked Faults in SRAMs (Abstract)

G. Di Natale , Politecnico di Torino, Italy
A. Bosio , Politecnico di Torino, Italy
A. Benso , Politecnico di Torino, Italy
S. Di Carlo , Politecnico di Torino, Italy
P. Prinetto , Politecnico di Torino, Italy
pp. 49-54

Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories (Abstract)

Jin-Fu Li , National Central University, Taiwan
Yu-Jen Huang , National Central University, Taiwan
pp. 55-62
Test of Reconfiguration Systems

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices (Abstract)

Hideo Ito , Chiba University, Japan
Kentaroh Katoh , Chiba University, Japan
pp. 69-74

Fault Injection-based Reliability Evaluation of SoPCs (Abstract)

M. Portela-Garcia , Universidad Carlos III de Madrid, Spain
M. Sonza Reorda , Politecnico di Torino, Italy
M. Violante , Politecnico di Torino, Italy
L. Sterpone , Politecnico di Torino, Italy
C. Lopez-Ongil , Universidad Carlos III de Madrid, Spain
L. Entrena , Universidad Carlos III de Madrid, Spain
pp. 75-82
Memory Testing - 2

Retention-Aware Test Scheduling for BISTed Embedded SRAMs (Abstract)

Qiang Xu , The Chinese University of Hong Kong
F. Y. Young , The Chinese University of Hong Kong
Baosheng Wang , ATI Technologies Inc., Canada
pp. 83-88

A Transparent based Programmable Memory BIST (Abstract)

Slimane Boutobza , Synopsys Inc, France
Michael Nicolaidis , Tima, France
Kheiredine M. Lamara , Synopsys Inc, France
Andrea Costa , Synopsys Inc, France
pp. 89-96
Test and Measurement

A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare (Abstract)

Bernd Laquai , Agilent Technologies, Germany
Guido Schulze , Agilent Technologies, Germany
Michael Braun , Agilent Technologies, Germany
Martin Hua , Agilent Technologies, Germany
pp. 97-102

On-Chip Time Measurement Architecture with Femtosecond Timing Resolution (Abstract)

Bashir M. Al-Hashimi , University of Southampton, UK
Matthew Collins , University of Southampton, UK
pp. 103-110
BIST and Test Data Compression for Logic

On-Chip Test Generation Using Linear Subspaces (Abstract)

Igor L. Markov , University of Michigan, USA
Ramashis Das , University of Michigan, USA
John P. Hayes , University of Michigan, USA
pp. 111-116

Convolutional Compactors with Variable Polynomials (Abstract)

Jerzy Tyszer , Poznan University of Technology, Poland
Artur Pogiel , Poznan University of Technology, Poland
Janusz Rajski , Mentor Graphics Corporation, USA
pp. 117-122

Deterministic Logic BIST for Transition Fault Testing (Abstract)

Hans-Joachim Wunderlich , Universitaet Stuttgart, Germany
Michael Garbers , Philips Semiconductors GmbH, Germany
Valentin Gherman , Universitaet Stuttgart, Germany
Juergen Schloeffel , Philips Semiconductors GmbH, Germany
pp. 123-130
Test of Sigma-Delta Modulators

Experimental Validation of a Fully Digital BISTfor Cascaded \Sigma \Delta Modulators (Abstract)

Adoraci? Rueda , Universidad de Sevilla, Spain
Gildas Leger , Instituto de Microelectr?nica de Sevilla (IMSE-CNM), Spain
pp. 131-136

Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits (Abstract)

Daniel Scain Farenzena , Universidade Federal do Rio Grande do Sul, Brazil
Luigi Carro , Universidade Federal do Rio Grande do Sul, Brazil
Erik Sch? , Universidade Federal do Rio Grande do Sul, Brazil
pp. 137-144
Current-Based and Power Switch Testing

Testing and Diagnosis of Power Switches in SOCs (Abstract)

Sandeep Kumar Goel , Philips Research Laboratories, The Netherlands
Jose Pineda de Gyvez , Philips Research Laboratories, The Netherlands
Maurice Meijer , Philips Research Laboratories, The Netherlands
pp. 145-150

A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications (Abstract)

T. Taris , IXL laboratory, France
Y. Deval , IXL laboratory, France
M. De Matos , IXL laboratory, France
H. Lapuyade , IXL laboratory, France
JB. B?gueret , IXL laboratory, France
M. Cimino , IXL laboratory, France
pp. 151-158
Test of AD and DA Circuits

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC (Abstract)

M. Comte , University of Montpellier, France
M. Renovell , University of Montpellier, France
P. Cauvet , Philips France Semiconducteurs, France
F. Aza? , University of Montpellier, France
S. Bernard , University of Montpellier, France
V. Kerz?rho , University of Montpellier, France
pp. 159-164

Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test (Abstract)

Abhijit Chatterjee , Georgia Insitute of Technology, USA
Mike Atia , National Semiconductor Corporation, USA
Shalabh Goyal, , Georgia Institute of Technology, USA
pp. 165-172
Automatic Test Pattern Generation

Fault Collapsing for Transition Faults Using Extended Transition Faults (Abstract)

Irith Pomeranz , Purdue University, USA
Sudhakar M. Reddy , University of Iowa, USA
pp. 173-178

FATE: a Functional ATPG to Traverse Unstabilized EFSMs (Abstract)

Cristina Marconcini , Universita di Verona, Italy
Franco Fummi , Universita di Verona, Italy
Giuseppe Di Guglielmo , Universita di Verona, Italy
Graziano Pravadelli , Universita di Verona, Italy
pp. 179-184

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults (Abstract)

S. M. Reddy , University of Iowa, USA
N. Devtaprasanna , University of Iowa, USA
A. Gunda , LSI Logic Inc., USA
I. Pomeranz , Purdue University, USA
P. Krishnamurthy , LSI Logic Inc., USA
pp. 185-192
Advanced Analog Testing

A Low Cost Alternative Method for Harmonics Estimation in a BIST Context (Abstract)

D. Dallet , Laboratoire IXL, France
S. Bernard , University of Montpellier, France
B. Agnus , Philips France Semiconducteurs, France
J.M. Janik , University of Caen, France
L. Bossuet , Laboratoire IXL, France
V. Fresnaud , Philips France Semiconducteurs, France
Ph. Gandy , Philips France Semiconducteurs, France
Ph. Cauvet , Philips France Semiconducteurs, France
pp. 193-198

Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters (Abstract)

Byoungho Kim , The University of Texas at Austin, USA
Jacob A. Abraham , The University of Texas at Austin, USA
Hongjoong Shin , The University of Texas at Austin, USA
Ji Hwan (Paul) Chun , Intel Corporation, AZ, USA
pp. 199-204

Low Cost Parametric Failure Diagnosis of RF Transceivers (Abstract)

Abhijit Chatterjee , Georgia Institute of Technology, USA
Soumendu Bhattacharya , Georgia Institute of Technology, USA
Donghoon Han , Georgia Institute of Technology, USA
Shalabh Goyal, , Georgia Institute of Technology, USA
pp. 205-212
Test of Asynchronous and NOC Circuitry

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism (Abstract)

Erik Jan Marinissen , Philips Research Laboratories, The Netherlands
Kees Goossens , Philips Research Laboratories, The Netherlands
Fernando Moraes , Catholic University - PUCRS, Brazil
Alexandre M. Amory , Federal University of RGS - UFRG, Brazil
Marcelo Lubaszewski , Federal University of RGS - UFRGS, Brazil
pp. 213-218

A DFT Architecture for Asynchronous Networks-on-Chip (Abstract)

Jean Durupt , LETI - CEA, France
Xuan-Tu Tran , LETI - CEA, France
Chantal Robach , LCIS - INPG, France
Vincent Beroulle , LCIS -INPG, France
Francois BERTRAND Bertrand , LETI - CEA, France
pp. 219-224

Low-Cost Online Testing of Asynchronous Handshakes (Abstract)

F. Burns , University of Newcastle upon Tyne, UK
D. Shang , University of Newcastle upon Tyne, UK
F. Xia , University of Newcastle upon Tyne, UK
A. Bystrov , University of Newcastle upon Tyne, UK
A. Yakovlev , University of Newcastle upon Tyne, UK
pp. 225-232
Diagnosis

Test-per-Clock Detection, Localization and Identification of Interconnect Faults (Abstract)

Krzysztof Gucwa , Silesian University of Technology, Poland
Michal Kopec , Silesian University of Technology, Poland
Andrzej Hlawiczka , Silesian University of Technology, Poland
Tomasz Garbolino , Silesian University of Technology, Poland
pp. 233-238

On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture (Abstract)

Matthias Beck , Infineon Technologies AG, Germany
Ralf Arnold , Infineon Technologies AG, Germany
Michael Goessel , University of Potsdam, Germany
Peter Ossimitz , Infineon Technologies AG, Germany
Frank Poehl , Infineon Technologies AG, Germany
Jan Rzeha , University of Potsdam, Germany
pp. 239-246
Embedded Tutorials

Soft-Error Rate Testing of Deep-Submicron Integrated Circuits (Abstract)

Tino Heijmen , Philips Research Laboratories, The Netherlands
Andr? Nieuwland , Philips Research Laboratories, The Netherlands
pp. 247-252

New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG) (Abstract)

Ben Bennetts , Bennetts Associates, UK
Bill Eklow , Cisco Systems, USA
pp. 253-254
Author Index

Author Index (PDF)

pp. 255
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