The Community for Technology Leaders
European Test Symposium (ETS'05) (2005)
Tallinn, Estonia
May 22, 2005 to May 25, 2005
ISSN: 1530-1877
ISBN: 0-7695-2341-2
SoC Testing

Energy Minimization for Hybrid BIST in a System-on-Chip Test Environment (Abstract)

Raimund Ubar , Tallinn University of Technology
Tatjana Shchenova , Tallinn University of Technology
Gert Jervan , Link?ping University
Zebo Peng , Link?ping University
pp. 2-7

Test Scheduling for Modular SOCs in an Abort-on-Fail Environment (Abstract)

Urban Ingelsson , Linköpings Universitet
Sandeep Kumar Goel , Philips Research Labs
Erik Larsson , Linköpings Universitet
Erik Jan Marinissen , Philips Research Labs
pp. 8-13

A New SoC Test Architecture with RF/Wireless Connectivity (Abstract)

Dan Zhao , University of Louisiana at Lafayette
Shambhu Upadhyaya , State University of New York at Buffalo
Martin Margala , University of Rochester
pp. 14-19
Advances in Fault and Defect Models

An Unified Fault Model and Test Generation Procedure for Interconnect Opens and Bridges (Abstract)

Gang Chen , University of Iowa
Sudhakar Reddy , University of Iowa
Irith Pomeranz , Purdue University
Janusz Rajski , Mentor Graphics Corporation
Piet Engelke , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
pp. 22-27

Defective Behaviours of Resistive Opens in Interconnect Lines (Abstract)

Daniel Arum? , Universitat Polit?cnica de Catalunya
Rosa Rodr?guez-Monta? , Universitat Polit?cnica de Catalunya
Joan Figueras , Universitat Polit?cnica de Catalunya
pp. 28-33

Testing of Resistive Opens in CMOS Latches and Flip-Flops (Abstract)

Victor H. Champac , National Institute for Astrophysics, Optics and Electronics
Antonio Zenteno , National Institute for Astrophysics, Optics and Electronics
José L. García , National Institute for Astrophysics, Optics and Electronics
pp. 34-40
Advanced Test Generation Issues

Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-At Test Generation (Abstract)

Tsuyoshi Iwagaki , Nara Institute of Science and Technology
Satoshi Ohtake , Nara Institute of Science and Technology
Hideo Fujiwara , Nara Institute of Science and Technology
pp. 48-53

Path-Oriented Transition Fault Test Generation Considering Operating Conditions (Abstract)

B. Seshadri , Purdue University
I. Pomeranz , Purdue University
S. M. Reddy , University of Iowa
S. Kundu , Intel Corporation
pp. 54-59
Low Cost Testing for Advanced Analog Circuits

Evaluation of Signature-Based Testing of RF/Analog Circuits (Abstract)

Amir Zjajo , Philips Research Laboratories
Jose Pineda de Gyvez , Philips Research Laboratories
pp. 62-67

Accurate Measurement of Multi-Tone Power Ratio (MTPR) of ADSL Devices Using Low Cost Testers (Abstract)

G. Srinivasan , Georgia Institute of Technology
S. Cherubal , Texas Instruments
P. Variyam , Texas Instruments
M. Teklu , Texas Instruments
C. P. Wang , Texas Instruments
D. Guidry , Texas Instruments
A. Chatterjee , Georgia Institute of Technology
pp. 68-73
On-Line and BIST Techniques for MEMS

Towards On-Line Testing of MEMS Using Electro-Thermal Excitation (Abstract)

F. Mailly , Université Montpellier II
F. Aza? , Université Montpellier II
N. Dumas , Université Montpellier II
L. Latorre , Université Montpellier II
P. Nouet , Université Montpellier II
pp. 76-81

Bias Superposition — An On-Line Test Strategy for a MEMS Based Conductivity Sensor (Abstract)

Carl Jeffrey , Lancaster University
Zhou Xu , Lancaster University
Andrew Richardson , Lancaster University
pp. 88-93
Defect and Dynamic Fault Testing

DOT: New Deterministic Defect-Oriented ATPG Tool (Abstract)

Jaan Raik , Tallinn University of Technology
Raimund Ubar , Tallinn University of Technology
Joachim Sudbrock , Tallinn University of Technology
Wieslaw Kuzmicz , Warsaw University of Technology
Witold Pleskacz , Warsaw University of Technology
pp. 96-101

Logic Circuits Testing for Transient Faults (Abstract)

Smita Krishnaswamy , University of Michigan
Igor L. Markov , University of Michigan
John P. Hayes , University of Michigan
pp. 102-107

A Novel Delay Fault Testing Methodology Using On-Chip Low-Overhead Delay Measurement Hardware at Strategic Probe Points (Abstract)

A. Raychowdhury , Purdue University
S. Ghosh , Purdue University
S. Bhunia , Purdue University
D. Ghosh , Purdue University
K. Roy , Purdue University
pp. 108-113
SRAM Memory Testing

Resistive-Open Defect Influence in SRAM Pre-Charge Circuits: Analysis and Characterization (Abstract)

Luigi Dilillo , Universté de Montpellier II
Patrick Girard , Universté de Montpellier II
Serge Pravossoudovitch , Universté de Montpellier II
Arnaud Virazel , Universté de Montpellier II
pp. 116-121

Automatic March Tests Generation for Static and Dynamic Faults in SRAMs (Abstract)

A. Benso , Politecnico di Torino
A. Bosio , Politecnico di Torino
S. Di Carlo , Politecnico di Torino
G. Di Natale , Politecnico di Torino
P. Prinetto , Politecnico di Torino
pp. 122-127

A Programmable Time Measurement Architecture for Embedded Memory Characterization (Abstract)

Matthew Collins , University of Southampton
Bashir M. Al-Hashimi , University of Southampton
Neil Ross , University of Southampton
pp. 128-133
Testing Regular Structures

Multiple Errors Produced by Single Upsets in FPGA Configuration Memory: A Possible Solution (Abstract)

Matteo Sonza Reorda , Politecnico di Torino
Luca Sterpone , Politecnico di Torino
Massimo Violante , Politecnico di Torino
pp. 136-141

Fault Collapsing for Flash Memory Disturb Faults (Abstract)

Mohammad Gh. Mohammad , Kuwait University
Laila Terkawi , Kuwait University
pp. 142-147

Low Power Embedded DRAMs with High Quality Error Correcting Capabilities (Abstract)

Philipp Öhler , University of Paderborn
Sybille Hellebrand , University of Paderborn
pp. 148-153
Validation and Molecular Electronics

Design Validation of Behavioral VHDL Descriptions for Arbitrary Fault Models (Abstract)

Fei Xin , University of Massachusetts at Amherst
Maciej Ciesielski , University of Massachusetts at Amherst
Ian G. Harris , University of California at Irvine
pp. 156-161

Coverage of Formal Properties Based on a High-Level Fault Model and Functional ATPG (Abstract)

Franco Fummi , Università di Verona
Graziano Pravadelli , Università di Verona
Franco Toto , STMicroelectronics
pp. 162-167
Fault Diagnosis

Convolutional Compaction-Driven Diagnosis of Scan Failures (Abstract)

Grzegorz Mrugalski , Mentor Graphics Corporation
Artur Pogiel , Poznań University of Technology
Janusz Rajski , Mentor Graphics Corporation
Jerzy Tyszer , Poznań University of Technology
Chen Wang , Mentor Graphics Corporation
pp. 176-181

Stuck-Open Fault Diagnosis with Stuck-At Model (Abstract)

Xinyue Fan , Oxford University
Will Moore , Oxford University
Camelia Hora , Philips Research Labs
Guido Gronthoud , Philips Research Labs
pp. 182-187
SoC Testing and Secure ICs

Test Control for Secure Scan Designs (Abstract)

David H?ly , ST Microelectronics and Universit? Montpellier II
Fr?d?ric Bancel , ST Microelectronics
Marie-Lise Flottes , Universit? Montpellier II
Bruno Rouzeyre , Universit? Montpellier II
pp. 190-195

Exploiting an Infrastructure IP to Reduce the Costs of Memory Diagnosis Costs in SoCs (Abstract)

P. Bernardi , Politecnico di Torino
M. Grosso , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
pp. 202-207
Embedded Tutorials

The Anatomy of Nanometer Timing Failures (Abstract)

Chuck Hawkins , University of New Mexico
Jaume Segura , University of the Balearic Islands
pp. 210-215

From Embedded Test to Embedded Diagnosis (Abstract)

Hans-Joachim Wunderlich , Universit?t Stuttgart
pp. 216-221

Test for Low Cost CMOS Image Sensors (PDF)

Peter Maxwell , Agilent Technologies
pp. 222

Testing of MEMS-Based Microsystems (Abstract)

Hans G. Kerkhoff , MESA+ Institute for Nanotechnology
pp. 223-228
Author Index

Author Index (PDF)

pp. 229-230
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